Branch Processor Registers; Machine State Register (Msr); Branch Processors Instructions; Fixed-Point Processor - Motorola MPC533 Reference Manual

Operating Environment Architecture (OEA)
3.15.1

Branch Processor Registers

3.15.1.1 Machine State Register (MSR)

ThefFloating-point exception mode encoding in the MPC533 core is as follows:
:
Table 3-23. Floating-Point Exception Mode Encoding
Ignore exceptions
Precise
Precise
Precise
The SF bit is reserved set to zero
The IP bit initial state after reset is set as programmed by the reset configuration as
specified by the USIU characteristics.

3.15.1.2 Branch Processors Instructions

The MPC533 implements all the instructions defined for the branch processor in the UISA
in the hardware.
3.15.2

Fixed-Point Processor

3.15.2.1 Special Purpose Registers

• Unsupported Registers — The following registers are not supported by the
MPC533: SDR, EAR, IBAT0U, IBAT0L, IBAT1U, IBAT1L, IBAT2U, IBAT2L,
IBAT3U, IBAT3L, DBAT0U, DBAT0L, DBAT1U, DBAT1L, DBAT2L, DBAT3U,
DBAT3L.
• Added Registers — For a list of added special purpose registers, refer to Table 3-2,
and Table 3-3.
3.15.3

Storage Control Instructions

Storage control Instructions mtsr, mtsrin, mfsr, mfsrin, dcbi, tlbie, tlbia, and tlbsync are not
implemented by the MPC533.
3.15.4

Exceptions

The following paragraphs define the types of OEA exceptions The exception table vector
defines the offset value by exception type. Refer to Table 3-21.
3-48
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Mode
MPC533 Reference Manual
FE0 FE1
0 0
0 1
1 0
1 1
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