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Queued Serial Peripheral Interface
been executed, asserting HALT does not set SPIF or clear SPE. QSPI execution continues
when the CPU clears HALT.
To stop the QSPI, assert the HALT bit in SPCR3, then wait until the HALTA bit in SPSR
is set. SPE can then be safely cleared, providing an orderly method of shutting down the
QSPI quickly after the current serial transfer is completed. The CPU can disable the QSPI
immediately by clearing SPE. However, loss of data from a current serial transfer may
result and confuse an external SPI device.
15.6.4.2 QSPI Interrupts
The QSPI has three possible interrupt sources but only one interrupt vector. These sources
are SPIF, MODF, and HALTA. When the CPU responds to a QSPI interrupt, the interrupt
cause must ascertained by reading the SPSR. Any interrupt that was set may then be cleared
by writing to SPSR with a zero in the bit position corresponding to the interrupt source.
The SPIFIE bit in SPCR2 enables the QSPI to generate an interrupt request upon assertion
of the SPIF status flag. Because it is buffered, the value written to SPIFIE applies only upon
completion of the queue (the transfer of the entry indicated by ENDPQ). Thus, if a single
sequence of queue entries is to be transferred (i.e., no WRAP), then SPIFIE should be set
to the desired state before the first transfer.
If a sub-queue is to be used, the same CPU write that causes a branch to the sub-queue may
enable or disable the SPIF interrupt for the sub-queue. The primary queue retains its own
selected interrupt mode, either enabled or disabled.
The SPIF interrupt must be cleared by clearing SPIF. Subsequent interrupts may then be
prevented by clearing SPIFIE. Clearing SPIFIE does not immediately clear an interrupt
already caused by SPIF.
15.6.4.3 QSPI Flow
The QSPI operates in either master or slave mode. Master mode is used when the MCU
initiates data transfers. Slave mode is used when an external device initiates transfers.
Switching between these modes is controlled by MSTR in SPCR0. Before entering either
mode, appropriate QSMCM and QSPI registers must be initialized properly.
In master mode, the QSPI executes a queue of commands defined by control bits in each
command RAM queue entry. Chip-select pins are activated, data is transmitted from the
transmit RAM and received by the receive RAM.
In slave mode, operation proceeds in response to SS pin assertion by an external SPI bus
master. Operation is similar to master mode, but no peripheral chip selects are generated,
and the number of bits transferred is controlled in a different manner. When the QSPI is
selected, it automatically executes the next queue transfer to exchange data with the
external device correctly.
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MPC533 Reference Manual
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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