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Paragraph
Number
11.6.2
L2U Reservation Support .............................................................................. 11-9
11.6.3
Reserved Location (Bus) and Possible Actions........................................... 11-10
11.7
L-Bus Show Cycle Support ..............................................................................11-11
11.7.1
Programming Show Cycles ..........................................................................11-11
11.7.2
Performance Impact......................................................................................11-11
11.7.3
Show Cycle Protocol ................................................................................... 11-12
11.7.4
L-Bus Write Show Cycle Flow.................................................................... 11-12
11.7.5
L-Bus Read Show Cycle Flow..................................................................... 11-12
11.7.6
Show Cycle Support Guidelines .................................................................. 11-13
11.8
L2U Programming Model................................................................................ 11-14
11.8.1
U-Bus Access............................................................................................... 11-14
11.8.2
Transaction Size........................................................................................... 11-15
11.8.3
L2U Module Configuration Register (L2U_MCR) ..................................... 11-15
11.8.4
Region Base Address Registers (L2U_RBAx)............................................ 11-15
11.8.5
Region Attribute Registers (L2U_RAx) ...................................................... 11-16
11.8.6
Global Region Attribute Register (L2U_GRA)........................................... 11-17
12.1
Features .............................................................................................................. 12-1
12.2
UIMB Block Diagram ....................................................................................... 12-2
12.3
Clock Module .................................................................................................... 12-2
12.4
Interrupt Operation ............................................................................................ 12-4
12.4.1
Interrupt Sources and Levels on IMB............................................................ 12-4
12.4.2
IMB Interrupt Multiplexing ........................................................................... 12-4
12.4.3
ILBS Sequencing ........................................................................................... 12-5
12.4.4
Interrupt Synchronizer ................................................................................... 12-6
12.5
Programming Model .......................................................................................... 12-7
12.5.1
UIMB Module Configuration Register (UMCR) .......................................... 12-8
12.5.2
Test Control Register (UTSTCREG)............................................................. 12-9
12.5.3
Pending Interrupt Request Register (UIPEND)............................................. 12-9
Queued Analog-to-Digital Converter Legacy Mode Operation
13.1
QADC64E Block Diagram ................................................................................ 13-1
13.2
Key Features, Overview, and Quick Reference Diagrams ................................ 13-2
13.2.1
Features of the QADC64E Legacy Mode Operation..................................... 13-2
13.2.2
Memory Map ................................................................................................. 13-3
13.2.3
Legacy and Enhanced Modes of Operation................................................... 13-4
13.2.4
Using the Queue and Result Word Table....................................................... 13-5
xiv
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Contents
Title
Chapter 12
U-Bus to IMB3 Bus Interface (UIMB)
Chapter 13
MPC533 Reference Manual
Page
Number
MOTOROLA
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