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17.11.8.1 MPIOSM Data Register (MPIOSMDR)
MSB
1
0
Field Data
Data
Data
15
14
13
Reset
Addr
Figure 17-31. MPIOSM Data Register (MPIOSMDR)
Bits
Name
15:0
DATA15–
These bits are read/write data bits that define the value to be driven to the pad in output mode,
DATA0
for each implemented I/O signal of the MPIOSM. The Msb is 15, Lsb is 0.
17.11.8.2 MPIOSM Data Direction Register (MPIOSMDDR)
MSB
1
0
Field DDR
DDR
DDR
15
14
13
Reset
Addr
Figure 17-32. MPIOSM Data Direction Register (MPIOSMDDR)
Bits
Name
0:15
DDR15–
These bits are read/write data bits that define the data direction status for each implemented I/O
DDR0
signal of the MPIOSM
0 = corresponding signal is input.
1 = corresponding signal is output.
17.12MIOS14 Interrupts
This section describes the interrupt functions of the MIOS14 and its submodules and how
these interrupts are passed to the CPU via the Peripheral bus. Interrupt requests from the
MIOS14 are treated as exceptions by the CPU and are dealt with by the CPU's exception
processing routines. For a more detailed description of exception processing in the relevant
microprocessors, please refer Chapter 3, "Central Processing Unit" and to the RCPU
Reference Manual (RCPURM/AD)
MOTOROLA
Chapter 17. Modular Input/Output Subsystem (MIOS14)
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2
3
4
5
Data
Data
Data
Data
12
11
10
Table 17-34. MPIOSMDR Bit Descriptions
2
3
4
5
DDR
DDR
DDR
DDR
12
11
10
Table 17-35. MPIOSMDDR Bit Descriptions
6
7
8
9
Data
Data
Data
Data
9
8
7
6
Undefined
0x30 6100
Description
6
7
8
9
DDR
DDR
DDR
DDR
9
8
7
6
Undefined
0x30 6100
Description
MIOS14 Interrupts
10
11
12
13
Data
Data
Data
Data
5
4
3
2
10
11
12
13
DDR
DDR
DDR
DDR
5
4
3
2
14
15
Data
1
0
14
15
DDR
1
0
17-63
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