Motorola MPC533 Reference Manual page 392

Chip-Select Timing
• The total cycle length = three clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— An extra clock cycle is required due to the effect of TRLX on the strobes.
CLOCK
Address
TS
TA
CS
RD/WR
WE/BE
OE
Data
In Figure 10-13, note the following:
• Because the TRLX bit is set, the assertion of the CS and WE strobes is delayed by
one clock cycle.
• Because ACS = 11, the assertion of CS is delayed an additional half clock cycle.
• Because CSNT = 1, WE is negated one clock cycle earlier than normal. (Refer to
Figure 10-8). The total cycle length is four clock cycles, determined as follows:
— The basic memory cycle requires two clock cycles.
— Two extra clock cycles are required due to the effect of TRLX on the assertion
and negation of the CS and WE strobes.
10-16
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
ACS = 00
Figure 10-12. Relaxed Timing — Write Access
(ACS = 10, SCY = 0, CSNT = 0, TRLX = 1)
MPC533 Reference Manual
ACS = 10
MOTOROLA