Motorola MPC533 Reference Manual page 41

Figure
Number
13-40 CCW Freeze Situation 16 ....................................................................................... 13-63
13-41 CCW Freeze Situation 17 ....................................................................................... 13-63
13-42 CCW Freeze Situation 18 ....................................................................................... 13-63
13-43 CCW Freeze Situation 19 ....................................................................................... 13-64
13-44 External Trigger Mode (Positive Edge) Timing with Pause ................................... 13-64
13-45 Gated Mode, Single-Scan Timing........................................................................... 13-66
13-46 Gated Mode, Continuous Scan Timing ................................................................... 13-67
13-47 Equivalent Analog Input Circuitry.......................................................................... 13-69
13-48 Errors Resulting from Clipping............................................................................... 13-70
13-49 Star-Ground at the Point of Power Supply Origin .................................................. 13-72
13-50 Electrical Model of an A/D Input Signal ................................................................ 13-73
13-51 External Multiplexing of Analog Signal Sources ................................................... 13-75
13-52 Input Signal Subjected to Negative Stress .............................................................. 13-78
13-53 Input Signal Subjected to Positive Stress................................................................ 13-78
14-1 QADC64E Block Diagram ....................................................................................... 14-2
14-2 CCW Queue and Result Table Block Diagram......................................................... 14-6
14-3 Example of External Multiplexing ........................................................................... 14-7
14-4 Module Configuration Register (QADCMCR)......................................................... 14-8
14-6 Interrupt Levels on IRQ with ILBS ........................................................................ 14-13
14-5 QADC Interrupt Register (QADCINT) .................................................................. 14-13
14-7 Port A Data Register (PORTQA)............................................................................ 14-14
14-8 Control Register 0 (QACR0) .................................................................................. 14-15
14-9 Control Register 1 (QACR1) ................................................................................. 14-17
14-10 Control Register 2 (QACR2) .................................................................................. 14-19
14-11 Status Register 0 (QASR0) ..................................................................................... 14-22
14-12 Queue Status Transition .......................................................................................... 14-27
14-13 Status Register 1 (QASR1) ..................................................................................... 14-28
14-14 QADC64E Conversion Queue Operation ............................................................... 14-30
14-15 Conversion Command Word Table (CCW) ............................................................ 14-32
14-16 Right Justified, Unsigned Result Format (RJURR) ................................................ 14-35
14-17 Left Justified, Signed Result Format (LJSRR) ....................................................... 14-35
14-18 Left Justified, Unsigned Result Register (LJURR)................................................. 14-35
14-19 QADC64E Analog Subsystem Block Diagram ...................................................... 14-36
14-20 Conversion Timing.................................................................................................. 14-37
14-21 QADC64E Queue Operation With Pause ............................................................... 14-40
14-22 QADC64E Clock Subsystem Functions ................................................................. 14-51
14-23 Bus Cycle Accesses ................................................................................................ 14-54
14-24 CCW Priority Situation 1........................................................................................ 14-57
14-25 CCW Priority Situation 2........................................................................................ 14-58
14-26 CCW Priority Situation 3........................................................................................ 14-58
14-27 CCW Priority Situation 4........................................................................................ 14-59
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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