Motorola MPC533 Reference Manual page 716

Programmer's Model
Signal RX1 RX0
X 0
CNRX0
X 1
TXMODE[1:0]
00
01
1X
1
Full CMOS drive indicates that both dominant and recessive levels are driven by the chip.
2
The CNRX1 signal is not available on the MPC533
3
Open drain drive indicates that only a dominant level is driven by the chip. During a recessive
level, the CNTX0 signal is disabled (three stated), and the electrical level is achieved by external
pull-up/pull-down devices. The assertion of both Tx mode bits causes the polarity inversion to
be cancelled (open drain mode forces the polarity to be positive).
16.7.5 Control Register 1 (CANCTRL1)
MSB 1 2
0
Field
SRESET
Addr
Bits Name
0:7 CANCTRL0 See Table 16-13
8 SAMP Sampling mode. The SAMP bit determines whether the TouCAN module will sample each
received bit one time or three times to determine its value.
0 One sample, taken at the end of phase buffer segment one, is used to determine the value
1 Three samples are used to determine the value of the received bit. The samples are taken
9 — Reserved
16-30
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 16-14. Rx MODE[1:0] Configuration
0 CNRX0 signal is interpreted as a dominant bit
1 CNRX0 signal is interpreted as a recessive bit
0 CNRX0 signal is interpreted as a recessive bit
1 CNRX0 signal is interpreted as a dominant bit
Table 16-15. Transmit Signal Configuration
TransmitSignal Configuration
1
Full CMOS ; positive polarity (CNTX0 = 0 is a dominant level)
1
Full CMOS ; negative polarity (CNTX0 = 1 is a dominant level)
3
Open drain ; positive polarity
3 4 5 6
CANCTRL0
0000_0000_0000_0000
0x30 7486 (CANCTRL1_B)
Figure 16-12. Control Register 1 (CANCTRL1)
Table 16-16. CANCTRL1 Bit Descriptions
of the received bit.
at the normal sample point and at the two preceding periods of the S-clock.
MPC533 Reference Manual
Receive Signal Configuration
7 8 9 10
SAMP — TSYNC LBUF
Description
2
2
11 12 13 14
— PROPSEG
MOTOROLA
LSB
15