Motorola MPC533 Reference Manual page 698

TouCAN Architecture
128, the FCS[1:0] field in the error status register is updated to be error active, and
both error counters are reset to zero. Any time a dominant bit is detected following
a stream of less than 11 consecutive recessive bits, the internal counter resets itself
to zero but does not affect the Tx error counter value.
• If only one node is operating in a system, the Tx error counter is incremented with
each message it attempts to transmit, due to the resulting acknowledgment errors.
However, acknowledgment errors never cause the TouCAN to change from the error
passive state to the bus off state.
• If the Rx error counter increments to a value greater than 127, it stops incrementing,
even if more errors are detected while being a receiver. After the next successful
message reception, the counter is reset to a value between 119 and 127, to enable a
return to the error active state.
The three basic states and the transition behavior of the CAN controller are shown in
Figure 16-6.
Error Active
Normal State
128 Occurences of 11 consecutive recessive bits,
Tx Error and Rx Error are reset to 0.
16.3.5 Time Stamp
The value of the free-running 16-bit timer is sampled at the beginning of the identifier field
on the CAN bus. For a message being received, the time stamp is stored in the time stamp
entry of the receive message buffer at the time the message is written into that buffer. For
a message being transmitted, the time stamp entry is written into the transmit message
buffer once the transmission has completed successfully.
The free-running timer can optionally be reset upon the reception of a frame into message
buffer 0. This feature allows network time synchronization to be performed.
16-12
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
(TX Error ≤ 127 AND RX Error ≤ 127)
(TX Error > 127 OR RX Error > 127) AND (TX Error < 255)
Figure 16-6. CAN Controller State Diagram
MPC533 Reference Manual
Error Passive
Bus Off
TX Error > 255
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