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Figure
Number
6-36
Real-Time Clock Register (RTC).............................................................................. 6-45
6-37
Real-Time Clock Alarm Register (RTCAL) ............................................................. 6-45
6-38
Periodic Interrupt Status and Control Register (PISCR) .......................................... 6-46
6-39
Periodic Interrupt Timer Count (PITC)..................................................................... 6-46
6-40
Periodic Interrupt Timer Register (PITR) ................................................................. 6-47
6-41
SGPIO Data Register 1 (SGPIODT1)....................................................................... 6-47
6-42
SGPIO Data Register 2 (SGPIODT2)....................................................................... 6-48
6-43
SGPIO Control Register (SGPIOCR) ....................................................................... 6-49
7-1
Reset Status Register (RSR) ....................................................................................... 7-6
7-2
Reset Configuration Basic Scheme............................................................................. 7-8
7-3
Reset Configuration Sampling Scheme For "Short" PORESET Assertion, Limp Mode
Disabled.................................................................................................................. 7-9
7-4
Reset Configuration Timing for
"Short" PORESET Assertion, Limp Mode Enabled............................................ 7-10
7-5
Reset Configuration Timing for
"Long" PORESET Assertion, Limp Mode Disabled ........................................... 7-10
7-6
Reset Configuration Sampling Timing Requirements .............................................. 7-11
7-7
Reset Configuration Word (RCW)............................................................................ 7-11
8-1
Clock Unit Block Diagram ......................................................................................... 8-2
8-2
Main System Oscillator Crystal Configuration........................................................... 8-3
8-3
System PLL Block Diagram ....................................................................................... 8-6
8-4
MPC533 Clocks .......................................................................................................... 8-8
8-5
General System Clocks Select .................................................................................. 8-11
8-6
Divided System Clocks Timing Diagram ................................................................. 8-12
8-7
Clocks Timing For DFNH = 1 (or DFNL = 0).......................................................... 8-13
8-8
Clock Source Switching Flow Chart......................................................................... 8-15
8-9
MPC533 Low-Power Modes Flow Diagram ............................................................ 8-21
8-10
Basic Power Supply Configuration........................................................................... 8-23
8-11
External Power Supply Scheme ................................................................................ 8-24
8-12
Keep-Alive Register Key State Diagram .................................................................. 8-26
8-13
System Clock and Reset Control Register (SCCR) .................................................. 8-30
8-14
PLL, Low-Power, and Reset-Control Register (PLPRCR)....................................... 8-34
8-15
Change of Lock Interrupt Register (COLIR)............................................................ 8-36
8-16
Control Register (VSRMCR)................................................................................... 8-37
9-1
Input Sample Window................................................................................................. 9-2
9-2
MPC533 Bus Signals .................................................................................................. 9-3
9-3
Basic Transfer Protocol............................................................................................... 9-8
9-4
Basic Flow Diagram of a Single Beat Read Cycle ..................................................... 9-9
9-5
Single Beat Read Cycle – Basic Timing – Zero Wait States .................................... 9-10
9-6
Single Beat Read Cycle – Basic Timing – One Wait State ....................................... 9-11
9-7
Basic Flow Diagram of a Single Beat Write Cycle................................................... 9-12
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Figures
Title
Figures
Page
Number
xxxvii
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