Motorola MPC533 Reference Manual page 666

Serial Communication Interface
3. If RXDx is high during this RT period, store sample and proceed to step 4.
4. If RXDx is low during this RT period, but not high for the previous three RT
periods (which is noise only), set an internal working noise flag and go to step 1,
since this transition was not a valid start bit transition.
5. If RXDx is low during this RT period and has been high for the previous three RT
periods, call this period RT1, set RAF, and proceed to step 6.
6. Skip RT2 but place RT3 in the pipeline and proceed to step 7.
7. Skip RT4 and sample RT5. If both RT3 and RT5 are high (RT1 was noise only), set
an internal working noise flag. Go to step 3 and clear RAF. Otherwise, place RT5 in
the pipeline and proceed to step 8.
8. Skip RT6 and sample RT7. If any two of RT3, RT5, or RT7 is high (RT1 was noise
only), set an internal working noise flag. Go to step 3 and clear RAF. Otherwise,
place RT7 in the pipeline and proceed to step 9.
9. A valid start bit is found and synchronization is achieved. From this point on until
the end of the frame, the RT clock will increment starting over again with RT1 on
each one-to-zero transition or each RT16. The beginning of a bit-time is thus
defined as RT1 and the end of a bit-time as RT16.
Upon detection of a valid start bit, synchronization is established and is maintained through
the reception of the last stop bit, after which the procedure starts all over again to search for
a new valid start bit. During a frame's reception, SCIx resynchronizes the RT clock on any
one-to-zero transitions.
Additional logic in the receiver bit processor determines the logic level of the received bit
and implements an advanced noise-detection function. During each bit-time of a frame
(including the start and stop bits), three logic-sense samples are taken at RT8, RT9, and
RT10. The logic sense of the bit-time is decided by a majority vote of these three samples.
This logic level is shifted into register RDRx for every bit except the start and stop bits.
If RT8, RT9, and RT10 do not all agree, an internal working noise flag is set. Additionally
for the start bit, if RT3, RT5, and RT7 do not all agree, the internal working noise flag is
set. If this flag is set for any of the bit-times in a frame, the NF flag in SCxSR is set
concurrently with the RDRF flag in SCxSR when the data is transferred to register RDRx.
The user must determine if the data received with NF set is valid. Noise on the RXDx pin
does not necessarily corrupt all data.
The operation of the receiver bit processor is shown in Figure 15-30. This example
demonstrates the search for a valid start bit and the synchronization procedure as outlined
above. The possibilities of noise durations greater than one bit-time are not considered in
this examples.
15-60
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC533 Reference Manual MOTOROLA