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PPM Registers
18.4 PPM Registers
18.4.1
Module Configuration Register (PPMMCR)
MSB
1
2
0
Field STOP
Reset
Addr
Figure 18-8. Module Configuration Register (PPMMCR)
Bits
Name
Stop Mode Enable. When the STOP bit is set and the PPM enters Stop Mode, the PPM module
clocks will be stopped. The PPM will only respond to accesses to the PPMMCR register. The
STOP bit can only be set when the PPM is disabled, (i.e., PPMPCR[ENTX] = 0 and
0
STOP
PPMPCR[ENRX] = 0). Writing to the STOP bit while either TX or RX is enabled will result in a
TEA (bus error access).
0 = PPM clocks enabled
1 = PPM clock disabled – PPM in Stop Mode.
1:7
—
Reserved
Supervisor/User Data Space. The SUPV bit places the PPM registers in either Supervisor or User
Data Space.
8
SUPV
0 = Access to PPMMCR, TX_CONFIG1/2, RX_CONFIG1/2 is restricted to supervisor-only.
1 = All PPM registers are accessible in supervisor-only data space.
9:15
—
Reserved
18.4.1.1 Entering Stop Mode
The PPM module cannot, and should not, be put into stop mode while either the transmit
or receive operation is enabled in PPMPCR[ENTX] and/or PPMPCR[ENRX].
The following steps should be taken to ensure that stop mode is entered safely and without
loss of data:
1. If the PPM is enabled for transmit or receive, set PPMPCR[STR] (TDM or SPI
mode).
2. Disable both PPMPCR[ENTX] and PPMPCR[ENRX]
3. Wait until PPMPCR[STR] is cleared by the PPM module. This will be done when
the next data frame has been sent or received.
4. Set PPMMCR[STOP]
18-10
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
3
4
5
6
RESERVED
0000_0000_0000_0000
Table 18-2. PPMMCR Bit Descriptions
Access to all other PPM registers is unrestricted.
MPC533 Reference Manual
7
8
9
10
SUPV
0x30 5C00
Description
11
12
13
14
LSB
RESERVED
MOTOROLA
15
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