Motorola MPC533 Reference Manual page 252

Memory Map and Register Definitions
6.2.2.2.9 Interrupt In-Service Registers (SISR2 and SISR3)
SISR2, SISR3 are 32-bit read/write registers. Each bit in the register corresponds to an
interrupt request. A bit is set if:
• There is a pending interrupt request (SIPEND2/3), that is not masked by (SIMASK2/3),
and
• The BBC/IMPU acknowledges interrupt request and latches SIVEC value.
Once a bit is set, all requests with lower or equal priority become masked (i.e. they will not
generate any interrupt request to the RCPU) until the bit is cleared. A bit is cleared by
writing a '1' to it. Writing zero has no effect.
MSB 1
0
Field IRQ0 LVL0 IMB
IRQ0
SRESET
16 17
Field IMB IMB IRQ3 LVL4
IRQ10 IRQ11
SRESET
Addr
MSB 1
0
Field IMB IMB
IRQ20 IRQ21
SRESET
16 17
Field
SRESET
Addr
6-38
2 3 4 5
IMB IMB IMB
IRQ1 IRQ2 IRQ3
18 19 20 21
IMB IMB
IRQ12 IRQ13
Figure 6-24. Interrupt In-Service Register 2 (SISR2)
2 3 4 5
IMB IMB IRQ LVL
IRQ22 IRQ23 6 6
18 19 20 21
Figure 6-25. Interrupt In-Service Register 3 (SISR3)
MPC533 Reference Manual
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
6 7 8 9
IRQ1 LVL1 IMB IMB
IRQ4 IRQ5
0000_0000_0000_0000
22 23 24 25
IMB IMB IRQ4 LVL4
IRQ14 IRQ15
0000_0000_0000_0000
0x2F C050
6 7 8
IMB IMB IMB IMB
IRQ24 IRQ25 IRQ26 IRQ27
0000_0000_0000_0000
22 23 24 25
—
0000_0000_0000_0000
0x2F C054
10 11 12
IMB IMB IRQ2
IRQ6 IRQ7
26 27 28
IMB IMB IMB
IRQ16 IRQ17 IRQ18 IRQ19
9 10 11 12 13
IRQ LVL IMB IMB
7 7 IRQ28 IRQ29
26 27 28 29
13 14 15
LVL2 IMB IMB
IRQ8 IRQ9
29 30 LSB
31
IMB IRQ5 LVL5
14 15
IMB IMB
IRQ30 IRQ31
30 LSB
31
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