Motorola MPC533 Reference Manual page 283

The equation for VCOOUT is:
When operating with the backup clock, the system clock (and
CLKOUT) is one-half of the ring oscillator frequency, (i.e., the
system clock is approximately 11 MHz). The time base and PIT
clocks will be twice the system clock frequency.
In the case of initial system power up, or if KAPWR is lost, an external circuit must assert
power on reset (PORESET). Once KAPWR is valid, PORESET must be asserted long
enough to allow the external oscillator to start up and stabilize for the device to come out
of reset in normal (non limp) mode.
If limp mode is enabled (by the MODCK[1:3] pins), and PORESET is negated before the
external oscillator has started up, the backup clock, BUCLK, will be used to clock the
device. The device will start to run in limp mode. Software can then switch the clock mode
from BUCLK to PLL. If an application requires that the device always comes out of reset
in normal mode, PORESET should be asserted long enough for the external oscillator to
start up. The maximum start-up time of an external oscillator is given in Appendix K,
"Electrical Characteristics" and PORESET should be asserted for this time and at least an
additional 100, 000 input clock cycles.
If limp mode is disabled at reset, a short reset of at least 3 µs is enough to obtain normal
chip operation, because the BUCLK will not start. The system will wait for the external
oscillator to start-up and stabilize.
The PLL will begin to lock once PORESET has been negated, assuming stable KAPWR
and VDDSYN power supplies and internal oscillator (or external clock). The PLL
maximum lock time is determined by the input clock to the phase comparator. The PLL
locks within 500 input clock cycles if the PLPRCR[MF] <= 4. The PLL locks within 1000
input clock cycles if PLPRCR[MF] >4. HRESET will be released 512 system clock cycles
after the PLL locks.
Whenever PORESET is asserted, the MF bits are set according to Table 8-1, and the
division factor high frequency (DFNH) and division factor low frequency (DFNL) bits in
SCCR are set to the value of 0 (÷1 for DFNH and ÷2 for DFNL).
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
OSCCLK
VCOOUT =
DIVF + 1
NOTE
Chapter 8. Clocks and Power Control
x (MF + 1) x 2
System PLL
8-5