Motorola MPC533 Reference Manual page 348

Bus Operations
Table 9-3 lists the patterns of the data transfer for write cycles when the MPC533 initiates
an access.
Transfer TSIZE[0:1]
Size
Byte
Half-word
Word
Note: "—" denotes a byte not driven during that write cycle.
9.5.7 Arbitration Phase
The external bus design provides for a single bus master at any one time, either the MPC533
or an external device. One or more of the external devices on the bus can have the capability
of becoming bus master for the external bus. Bus arbitration may be handled either by an
external central bus arbiter or by the internal on-chip arbiter. In the latter case, the system
is optimized for one external bus master besides the MPC533. The arbitration configuration
(external or internal) is set at system reset.
Each bus master must have bus request (BR), bus grant (BG), and bus busy (BB) signals.
The device that needs the bus asserts BR. The device then waits for the arbiter to assert BG.
In addition, the new master must look at BB to ensure that no other master is driving the
bus before it can assert BB to assume ownership of the bus. Any time the arbiter has taken
the bus grant away from the master and the master wants to execute a new cycle, the master
must re-arbitrate before a new cycle can be executed. The MPC533, however, guarantees
data coherency for access to a small port size and for decomposed bursts. This means that
the MPC533 will not release the bus before the completion of the transactions that are
considered atomic. Figure 9-24 describes the basic protocol for bus arbitration.
9-32
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 9-3. Data Bus Contents for Write Cycles
Address
ADDR
[30:31]
01 00
01 01
01 10
01 11
10 00
10 10
00 00
MPC533 Reference Manual
External Data Bus Pattern
DATA DATA
[0:7] [8:15]
OP0 —
OP1 OP1
OP2 —
OP3 OP3
OP0 OP1
OP2 OP3
OP0 OP1
DATA DATA
[16:23] [24:31]
— —
— —
OP2 —
— OP3
— —
OP2 OP3
OP2 OP3
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