Motorola MPC533 Reference Manual page 293

If the LME bit is clear, the switch to the backup clock is disabled and assertion of STBUC
bit is ignored. If the chip is in limp mode, clearing the LME bit switches the system to
normal operation and asserts hard reset to the chip.
Figure 8-8 describes the clock switching control logic. Table 8-3 summarizes the status and
control for each state.
buclk_enable = 1
& hreset_b = 0
else
Figure 8-8. Clock Source Switching Flow Chart
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
1,BUCLK
poreset_b = 1
LME = 1
2,BUCLK
buclk_enable=0
& hreset_b=0
3,BUCLK
buclk_enable = 1
& hreset_b = 0
6,BULCK
Chapter 8. Clocks and Power Control
else
LME = 0
hreset_b = 0
4, osc
buclk_enable = 0
& hreset_b = 0
5, osc
Clock Source Switching
LOCS=0
else
8-15