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11.5.2
Associated Registers
Table 11-1 shows registers that are used to control the DMPU of the L2U module. All the
registers are special purpose registers that are accessed via the MPC500 mtspr/mfspr
instructions. The registers are also accessed by an external master when
EMCR[CONT] = 0. See Section 11.8, "L2U Programming Model," for register diagrams
and bit descriptions.
.
L2U_RBA0
L2U_RBA1
L2U_RBA2
L2U_RBA3
The appropriate DMPU registers must be programmed before
the MSR[DR] bit is set. Otherwise, DMPU operation is not
guaranteed.
Program the region base address in the L2U_RBAx registers to the lower boundary of the
region specified by the corresponding L2U_RAx[RS] field. If the region base address does
not correspond to the boundary of the block size programmed in the L2U_RAx, the DMPU
snaps the region base to the lower boundary of that block. For example, if the block size is
programmed to 16 Kbytes for region zero (i.e., L2U_RA0[RS] = 0x3) and the region base
address is programmed to 0x1FFF(i.e., L2U_RBA0[RBA] = 0x1), then the effective base
address of region zero is 0x0. See Figure 11-3.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 11-1. DMPU Registers
Name
Region Base Address Register 0
Region Base Address Register 1
Region Base Address Register 2
Region Base Address Register 3
L2U_RA0
L2U_RA1
L2U_RA2
L2U_RA3
L2U_GRA
Chapter 11. L-Bus to U-Bus Interface (L2U)
Description
Region Attribute Register 0
Region Attribute Register 1
Region Attribute Register 2
Region Attribute Register 3
Global Region Attribute
NOTE
Data Memory Protection
11-7
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