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Development Port
is asserted before the next fetch occurs to allow the development system to detect the
excepting instruction.
Not all exceptions are recognized when in debug mode. Breakpoints and watchpoints are
not generated by the hardware when in debug mode (regardless of the value of MSR[RI]).
Upon entering debug mode MSR[EE] is cleared by the hardware thus forcing the hardware
to ignore external and decrementer interrupts.
Setting the MSR[EE] bit while in debug mode, (by the debug
software), is strictly forbidden. The reason for this restriction is
that the external interrupt event is a level signal, and since the
CPU only reports exceptions while in debug mode but do not
treat them, the CPU does not clear the MSR[EE] bit and,
therefore, this event, if enabled, is recognized again every
clock cycle.
When the ecr_or signal is asserted the development station should investigate the exception
cause register (ECR) in order to find out the event that caused the exception.
Since the values in SRR0 and SRR1 do not change if an exception is recognized while
already in debug mode, they only change once when entering debug mode, saving them
when entering debug mode is not necessary.
21.3.1.6 Exiting Debug Mode
The rfi instruction is used to exit from debug mode in order to return to the normal
processor operation and to negate the freeze indication. The development system may
monitor the freeze status to make sure the MPC533 is out of debug mode. It is the
responsibility of the software to read the exception cause register (ECR) before performing
the rfi. Failing to do so will force the CPU to immediately re-enter to debug mode and to
re-assert the freeze indication in case an asserted bit in the interrupt cause register (ECR)
has a corresponding enable bit set in the debug enable register (DER).
21.4 Development Port
The development port provides a full duplex serial interface for communications between
the internal development support logic including debug mode and an external development
tool.
The relationship of the development support logic to the rest of the CPU chip is shown in
Figure 21-6. The development port support logic is shown as a separate block for clarity. It
is implemented as part of the SIU module.
21-34
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
WARNING
MPC533 Reference Manual
MOTOROLA
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