Motorola MPC533 Reference Manual page 920

Development Support Registers
Table 21-21. ECR Bit Descriptions (continued)
Bits Name
11:12 — Reserved
13 SYSE System call exception bit. Set when the system call exception is asserted.
14 TR Trace exception bit. Set when in single-step mode or when in branch trace mode.
15 FPASE Floating point assist exception bit. Set when the floating point assist exception occurs.
16 — Reserved
17 SEE Software emulation exception. Set when the software emulation exception is asserted.
18 — Reserved
19 ITLBER Implementation specific instruction protection error
This bit is set as a result of an instruction protection error. Results in debug mode entry if debug
mode is enabled and the corresponding enable bit is set.
20 — Reserved
21 DTLBER Implementation specific data protection error
This bit is set as a result of an data protection error. Results in debug mode entry if debug mode
is enabled and the corresponding enable bit is set.
22:27 — Reserved
28 LBRK L-bus breakpoint exception bit. This bit is set as a result of the assertion of a load/store
breakpoint. Results in debug mode entry if debug mode is enabled and the corresponding enable
bit is set.
29 IBRK I-bus breakpoint exception bit. This bit is set as a result of the assertion of an Instruction
breakpoint. Results in debug mode entry if debug mode is enabled and the corresponding enable
bit is set.
30 EBRK External breakpoint exception bit. Set when an external breakpoint is asserted (by an on-chip IMB
or L-bus module, or by an external device or development system through the development port).
This bit is set as a result of the assertion of an external breakpoint. Results in debug mode entry
if debug mode is enabled and the corresponding enable bit is set.
31 DPI Development port interrupt bit. Set by the development port as a result of a debug station
non-maskable request or when debug mode is entered immediately out of reset.
21.6.4 Debug Enable Register (DER)
This register enables selectively masking the events that may cause the processor to enter
into debug mode.
21-50
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Description
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