Floating-Point Unit (Fpu); Levels Of The Mpc500 Architecture - Motorola MPC533 Reference Manual

3.4.4

Floating-Point Unit (FPU)

The FPU contains a double-precision multiply array, the floating-point status and control
register (FPSCR), and the FPRs. The multiply-add array allows the MPC533 to efficiently
implement floating-point operations such as multiply, multiply-add, and divide.
The MPC533 depends on a software envelope to fully implement the IEEE floating-point
specification. Overflows, underflows, NaNs (not a number), and denormalized numbers
cause floating-point assist exceptions that invoke a software routine to deliver (with
hardware assistance) the correct IEEE result.
To accelerate time-critical operations and make them more deterministic, the MPC533
provides a mode of operation that avoids invoking the software envelope and attempts to
deliver results in hardware that are adequate for most applications, if not in strict
compliance with IEEE standards. In this mode, denormalized numbers, NaNs, and IEEE
invalid operations are legitimate, returning default results rather than causing floating-point
assist exceptions.
3.5

Levels of the MPC500 Architecture

The MPC500 is designed from a PowerPC-like architecture that consists of three levels.
Adherence to the MPC500 architecture can be measured in terms of which of the following
levels are implemented:
• User instruction set architecture (UISA) — defines the base user-level instruction
set, user-level registers, data types, floating-point exception model, memory models
for a uniprocessor environment, and programming model for a uniprocessor
environment.
• Virtual environment architecture (VEA) — describes the memory model for a
multiprocessor environment, and describes other aspects of virtual environments.
Implementations that conform to the VEA also adhere to the UISA, but may not
necessarily adhere to the OEA.
• Operating environment architecture (OEA) — defines the memory-management
model, supervisor-level registers, synchronization requirements, and the exception
model. Implementations that conform to the OEA also adhere to the UISA and the
VEA.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chapter 3. Central Processing Unit
Levels of the MPC500 Architecture
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