Motorola MPC533 Reference Manual page 192

Exception Table Relocation (ETR)
the higest priority interrupt request from a peripherial module or external interrupt request
pin. See Figure 4-3.
The external interrupt relocation table should be placed at the physical address defined in
the external interrupt relocation table base address register. See Section 4.6.2.5, "External
Interrupt Relocation Table Base Address Register (EIBADR)."
Each table entry must contain a branch absolute (ba) instruction to the first instruction of
an interrupt service routine. Each table entry occupies two words (eight bytes) to support
decompression on mode, where a branch instruction can be more than 32 bits long.
The memory space allocated for the external interrupt relocation table is up to 2 Kbytes. If
part of the external interrupt relocation table entries is not used, it may be utilized for
another purpose as either instruction code space or data space.
In order to activate the external interrupt relocation feature, the following steps are
required:
1. Program the EIBADR register to the external interrupt branch table base address.
See Section 4.6.2.5, "External Interrupt Relocation Table Base Address Register
(EIBADR)."
2. Set the MSR[IP] bit.
3. Set the BBCMCR[EIR] bit. See Section 4.6.2.1, "BBC Module Configuration
Register (BBCMCR)," for programming details.
4. Set SIUMCR[EIC] bit. See Section 6.1.4.4, "Enhanced Interrupt Controller
Operation."
If both the enhanced external interrupt relocation and exception
table relocation functions are activated simultaneously, the
final external interrupt vector is defined by EEIR mechanism.
When the EEIR function is activated, any branch instruction
execution with the 0xFFF0_0500 target address may cause
unpredictable program execution.
4-10
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
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