Motorola MPC533 Reference Manual page 298

Low-Power Modes
frequency clocks. For a PLL input frequency of four MHz, the wake-up time is less than
125 µs.
8.7.3.4 Exiting from Power-Down Mode
Exit from power-down mode is accomplished through hard reset. External logic should
assert HRESET in response to the TEXPS bit being set and TEXP pin being asserted. The
TEXPS bit is set by an enabled RTC, PIT, time base, or decrementer interrupt. The hard
reset should be asserted for no longer than the time it takes for the power supply to wake-up
in addition to the PLL lock time. When the TEXPS bit is cleared (and the TEXP signal is
negated), assertion of hard reset sets the bit, causes the pin to be asserted, and causes an exit
from power-down low-power mode. Refer to Section 8.8.3, "Keep-Alive Power" for more
information.
8.7.3.5 Low-Power Modes Flow
Figure 8-9 shows the flow among the different power modes.
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC533 Reference Manual MOTOROLA