Motorola MPC533 Reference Manual page 939

22.0.7 Terms and Definitions
Term
Auxiliary Port Refers to IEEE-ISTO 5001 auxiliary port.
Branch Trace Messaging External visibility of addresses for taken branches and exceptions, and the number of
(BTM) sequential instructions executed between each taken branch.
BDM Background Debug Mode.
Compressed Code Mode Current instruction stream is fetching compressed code. Available in only.
Calibration Constants Performance related constants which must be tuned for automotive powertrain and disk drive
applications.
Calibration Variables Intermediate calculations which must be visible during the calibration or tuning process to
enable accurate tuning of calibration constants.
Data Read Message External visibility of data reads to internal memory-mapped resources.
(DRM)
Data Write Message External visibility of data writes to internal memory-mapped resources.
(DWM)
Data Trace Messaging External visibility of how data flows through the embedded system. May include DRM and/or
(DTM) DWM.
Download Tool sends information to the device
Field Number of bits representing single piece of information
FPM Full Port Mode. This is the default full port mode for READI.
IEEE-ISTO 5001 IEEE-ISTO 5001, formerly known as Global Embedded Processor Debug Interface Standard.
Worldwide web documentation at http://www.nexus5001.org/.
Halt RCPU is in freeze state (typically in debug mode)
Instruction Fetch The process of reading the instruction data received from the instruction memory.
Instruction Issue The process of driving valid instruction bits inside the processor. The instruction is decoded
by each execution unit, and the appropriate execution unit prepares to execute the instruction
during the next clock cycle.
Instruction Taken An instruction is taken after it has been issued and recognized by the appropriate execution
unit. All resources to perform the instruction are ready, and the processor begins to execute it.
Instruction Retire Completion of the instruction issue, execution and writeback stages. An instruction is ready
to be retired if it completes without generating an exception and all instructions ahead of it in
history buffer have completed without generating an exception.
ICTRL Instruction bus support control register (Refer to Table 21.6.11)
Ownership Trace Visibility of process/function that is currently executing.
Message (OTM)
Public Messages Messages on the auxiliary signals for accomplishing common visibility and controllability
requirements e.g. DRM and DWM.
RCPU Processor that implements the PowerPC-based architecture used in the Motorola MPC500
family of microcontrollers.
READI Real time Embedded Applications Development Interface.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 22-3. Terms and Definitions
Chapter 22. READI Module
Description
22-7