Table of Contents
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Figure
Number
K-34
Reset Timing – Configuration from Data Bus ..........................................................E-49
K-35
Reset Timing – Data Bus Weak Drive During Configuration ..................................E-50
K-36
Reset Timing – Debug Port Configuration ...............................................................E-51
K-37
JTAG Test Clock Input Timing .................................................................................E-52
K-38
JTAG Test Access Port Timing Diagram ..................................................................E-53
K-39
Boundary Scan (JTAG) Timing Diagram .................................................................E-54
K-40
QSPI Timing – Master, CPHA = 0 ...........................................................................E-59
K-41
QSPI Timing – Master, CPHA = 1 ...........................................................................E-60
K-42
QSPI Timing – Slave, CPHA = 0..............................................................................E-60
K-43
QSPI Timing – Slave, CPHA = 1..............................................................................E-61
K-44
MCPSM Enable to VS_PCLK Pulse Timing Diagram.............................................E-62
K-45
MPWMSM Minimum Output Pulse Example Timing Diagram ..............................E-63
K-46
MCPSM Enable to MPWMO Output Pin Rising Edge Timing Diagram ................E-64
K-47
MPWMSM Enable to MPWMO Output Pin Rising Edge Timing Diagram............E-64
K-48
MPWMSM Interrupt Flag To MPWMO Output Pin Falling Edge
Timing Diagram ...................................................................................................E-64
K-49
MMCSM Minimum Input Pin (Either Load Or Clock) Timing Diagram ................E-65
K-50
MMCSM Clock Pin To Counter Bus Increment Timing Diagram ...........................E-66
K-51
MMCSM Load Pin To Counter Bus Reload Timing Diagram .................................E-66
K-52
MMCSM Counter Bus Reload To Interrupt Flag Setting Timing Diagram .............E-66
K-53
MMCSM Prescaler Clock Select To Counter Bus Increment
Timing Diagram ...................................................................................................E-67
K-54
MDASM Minimum Input Pin Timing Diagra ..........................................................E-68
K-55
MDASM Input Pin To Counter Bus Capture Timing Diagram ................................E-68
K-56
MDASM Input Pin to MDASM Interrupt Flag Timing Diagram.............................E-68
K-57
MDASM Minimum Output Pulse Width Timing Diagram ......................................E-69
K-58
Counter Bus to MDASM Output Pin Change Timing Diagram ...............................E-69
K-59
Counter Bus to MDASM Interrupt Flag Setting Timing Diagram ...........................E-69
K-60
MPIOSM Input Pin to MPIOSM_DR (Data Register) Timing Diagram .................E-70
K-61
MPC533 Package Footprint (1 of 2) .........................................................................E-72
K-62
MPC533 Package Footprint (2 of 2) .........................................................................E-73
K-63
MPC533 Pinout Diagram..........................................................................................E-75
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Figures
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