Motorola MPC533 Reference Manual page 762

MIOS14 Double Action Submodule (MDASM)
Table 17-18. MDASM PWM Example Output Frequencies/Resolutions
Resolution
(bits)
16
16
15
15
14
14
13
13
12
12
11
11
9
9
7
7
1
This information is valid only if the MDASM is connected to an MMCSM operating as a free-running
counter.
When using 16 bits of resolution on the comparator (MODE[2:0] = 0b000), the output can
vary from a 0% duty cycle up to a duty cycle of 65535/65536. In this case it is not possible
to have a 100% duty cycle. In cases where 16-bit resolution is not needed, it is possible to
have a duty cycle ranging from 0% to 100%. Setting bit 15 of the value stored in register B
to one results in the output being 'always set'. Clearing bit 15 (to zero) allows normal
comparisons to occur and the normal output waveform is obtained. Changes to and from
the 100% duty cycle are done synchronously on an A or B match, as are all other width
changes.
In the OPWM mode, the WOR bit selects whether the output is totem pole driven or
open-drain.
17.9.6 Modular I/O Bus (MIOB) Interface
• The MDASM is connected to all the signals in the read/write and control bus, to
allow data transfer from and to the MDASM registers, and to control the MDASM
in the different possible situations.
17-38
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
at f
SYS
N N
MCPSM COUNTER
16 256
2 1
16 256
2 1
16 256
2 1
16 256
2 1
16 256
2 1
16 256
2 1
16 256
2 1
16 256
2 1
MPC533 Reference Manual
= 40 MHz
N PWM output frequency (Hz)
MDASM
65536
65536
32768
32768
16384
16384
8192
8192
4096
4096
2048
2048
512
512
128
128
1
0.15
305.17
0.29
610.35
0.59
1 220.70
1.19
2 441.41
2.38
4 882.81
4.77
9 765.63
19.07
39 062.50
76.29
156 250
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