Table of Contents
Advertisement
Development System Interface
Debug mode is enabled by asserting DSCK during reset. The state of this pin is sampled
three clocks before the negation of SRESET.
Because SRESET negation is done by an external pull up
resistor any reference here to SRESET negation time refers to
the time the MPC533 releases SRESET. If the actual negation
is slow due to a large resistor, set up time for the debug port
signals should be set accordingly.
If the DSCK pin is sampled negated, debug mode is disabled until a subsequent reset when
the DSCK pin is sampled in the asserted state. When debug mode is disabled the internal
watchpoint/breakpoint hardware will still be operational and may be used by a software
monitor program for debugging purposes.
When debug mode is disabled, all development support registers (see list in Table 21-17)
are accessible to the supervisor code (MSRPR = 0) and can be used by a monitor debugger
software. However, the processor never enters debug mode and, therefore, the exception
cause register (ECR) and the debug enable register (DER) are used only for asserting and
negating the freeze signal. For more information on the software monitor debugger support
refer to Section 21.5, "Software Monitor Debugger Support."
When debug mode is enabled, all development support registers are accessible only when
the CPU is in debug mode. Therefore, even supervisor code that may be still under debug
cannot prevent the CPU from entering debug mode. The development system has full
control of all development support features of the CPU through the development port. Refer
to Table 21-19.
21.3.1.2 Entering Debug Mode
Entering debug mode can be a result of a number of events. All events have a
programmable enable bit to selectively decide which events result in debug mode entry and
which in regular interrupt handling.
Entering debug mode is also possible immediately out of reset, thus allowing the debugging
of even a ROM-less system. Using this feature is possible by special programming of the
development port during reset. If the DSCK pin continues to be asserted following
SRESET negation (after enabling debug mode) the processor will take a breakpoint
exception and go directly to debug mode instead of fetching the reset vector. To avoid
entering debug mode following reset, the DSCK pin must be negated no later than seven
clock cycles after SRESET negates. In this case, the processor will jump to the reset vector
and begin normal execution. When entering debug mode immediately after reset, bit 31
(development port interrupt) of the exception cause register (ECR) is set.
21-30
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
MPC533 Reference Manual
MOTOROLA
Advertisement
Table of Contents
