Motorola MPC533 Reference Manual page 498

Trigger and Queue Interaction Examples
32-bit accesses to an even address require two bus cycles to complete the access, and two
full 16-bit QADC64E locations are accessed. The first bus cycle reads or writes the
addressed 16-bit QADC64E location and the second cycle reads or writes the following
16-bit location.
32-bit accesses to an odd address require three bus cycles. Portions of three different
QADC64E locations are accessed. The first bus cycle is treated by the QADC64E as an
8-bit access of an odd address, the second cycle is a 16-bit aligned access, and the third
cycle is an 8-bit access of an even address. The QADC64E address space is organized into
16-bit even address locations, so a 32-bit read or write of an odd address provides the lower
half of one QADC64E location, the full 16-bit content of the following QADC64E location,
and the upper half of the third QADC64E location.
13.6 Trigger and Queue Interaction Examples
This section contains examples describing queue priority and conversion timing schemes.
13.6.1 Queue Priority Schemes
Since there are two conversion command queues and only one A/D converter, there is a
priority scheme to determine which conversion is to occur. Each queue has a variety of
trigger events that are intended to initiate conversions, and they can occur asynchronously
in relation to each other and other conversions in progress. For example, a queue can be idle
awaiting a trigger event, a trigger event can have occurred but the first conversion has not
started, a conversion can be in progress, a pause condition can exist awaiting another trigger
event to continue the queue, and so on.
The following paragraphs and figures outline the prioritizing criteria used to determine
which conversion occurs in each overlap situation.
The situations in Figure 13-25 through Figure 13-43 are
labeled S1 through S19. In each diagram, time is shown
increasing from left to right. The execution of queue 1 and
queue 2 (Q1 and Q2) is shown as a string of rectangles
representing the execution time of each CCW in the queue. In
most of the situations, there are four CCWs (labeled C1 to C4)
in both queue 1 and queue 2. In some of the situations, CCW
C2 is presumed to have the pause bit set, to show the
similarities of pause and end-of-queue as terminations of queue
execution.
Trigger events are described in Table 13-14.
13-54
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
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