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Digital Subsystem
14.5.4.3.2 External Trigger Single-Scan Mode
The external trigger single-scan mode is available on both queue 1 and queue 2. The
software programs the polarity of the external trigger edge that is to be detected, either a
rising or a falling edge. The software must enable the scan to occur by setting the
single-scan enable bit for the queue.
The first external trigger edge causes the queue to be executed one time. Each CCW is read
and the indicated conversions are performed until an end-of-queue condition is
encountered. After the queue is completed, the QADC64E clears the single-scan enable bit.
Software may set the single-scan enable bit again to allow another scan of the queue to be
initiated by the next external trigger edge.
The external trigger single-scan mode is useful when the input trigger rate can exceed the
queue execution rate. Analog samples can be taken in sync with an external event, even
though the software is not interested in data taken from every edge. The software can start
the external trigger single-scan mode and get one set of data, and at a later time, start the
queue again for the next set of samples.
When a pause bit is encountered during external trigger single-scan mode, another trigger
event is required for queue execution to continue. Software involvement is not needed to
enable queue execution to continue from the paused state.
14.5.4.3.3 External Gated Single-Scan Mode
The QADC64E provides external gating for queue 1 only. When external gated single-scan
mode is selected, the input level on the associated external trigger signal enables and
disables queue execution. The polarity of the external gated signal is fixed so only a high
level opens the gate and a low level closes the gate. Once the gate is open, each CCW is
read and the indicated conversions are performed until the gate is closed. Software must
enable the scan to occur by setting the single-scan enable bit for queue 1. If a pause in a
CCW is encountered, the pause flag will not set, and execution continues without pausing.
While the gate is open, queue 1 executes one time. Each CCW is read and the indicated
conversions are performed until an end-of-queue condition is encountered. When queue 1
completes, the QADC64E sets the completion flag (CF1) and clears the single-scan enable
bit. Software may set the single-scan enable bit again to allow another scan of queue 1 to
be initiated during the next open gate.
If the gate closes before queue 1 completes execution, the current CCW completes,
execution of queue 1 stops, the single-scan enable bit is cleared, and the PF1 bit is set.
Software can read the CWPQ1 to determine the last valid conversion in the queue. Software
must set the single-scan enable bit again and should clear the PF1 bit before another scan
of queue 1 is initiated during the next open gate. The start of queue 1 is always the first
CCW in the CCW table.
MOTOROLAChapter 14. Queued Analog-to-Digital Converter Enhanced Mode Operation
14-45
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
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