Motorola MPC533 Reference Manual page 873

external devices. Or, they can generate address-only cycles when the instructions reside in
one of the internal devices (internal memory, etc.).
When VSYNC is asserted, some performance degradation is expected due to the additional
external bus cycles. However, since this performance degradation is expected to be very
small, it is possible to program the machine to show all indirect flow changes. In this way,
the machine will always perform the additional external bus cycles and maintain exactly
the same behavior both when VSYNC is asserted and when it is negated. For more
information refer to Section 21.6.10, "L-Bus Support Control Register 2."
The status pins are divided into two groups and one special case listed below:
21.1.1.1 Instruction Queue Status Pins — VF [0:2]
Instruction queue status pins denote the type of the last fetched instruction or how many
instructions were flushed from the instruction queue. These status pins are used for both
functions because queue flushes only happen in clocks that there is no fetch type
information to be reported.
Possible instruction types are defined in Table 21-1.
VF[0:2]
000 None
001 Sequential
010 Branch (direct or indirect) not taken
011 VSYNC was asserted/negated and therefore the next
instruction will be marked with the indirect
change-of-flow attribute
100 Exception taken — the target will be marked with the
indirect change-of-flow attribute
101 Branch indirect taken, rfi, mtmsr, isync and in some
cases mtspr to CMPA-F, ICTRL, ECR, or DER — the
target will be marked with the indirect change-of-flow
2
attribute
110 Branch direct taken
111 Branch (direct or indirect) not taken
1
Unless next clock VF=111. See below.
2
The sequential instructions listed here affect the machine in a manner similar to indirect branch instructions. Refer
to Section 21.1.3, "Sequential Instructions Marked as Indirect Branch."
Table 21-2 shows VF[0:2] encodings for instruction queue flush information.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 21-1. VF Pins Instruction Encodings
Instruction Type
Chapter 21. Development Support
Program Flow Tracking
VF Next Clock Will Hold
More instruction type information
More instruction type information
More instruction type information
More instruction type information
1
Queue flush information
1
Queue flush information
1
Queue flush information
1
Queue flush information
21-3