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21.6.12 Breakpoint Address Register (BAR)
Msb
1
2
3
4
0
Field
Reset
Addr
Figure 21-25. Breakpoint Address Register (BAR)
Bits
Mnemonic
0:31
BARV[0:31]
21.6.13 Development Port Data Register (DPDR)
This 32-bit special purpose register physically resides in the development port logic. It is
used for data interchange between the core and the development system. An access to this
register is initiated using mtspr and mfspr (SPR 630) and implemented using a special bus
cycle on the internal bus.
DPDR stores DSDO messages. It is a register for BDM communications outside of the
device.
Msb
1
2
3
4
0
Field
Reset
Addr
Figure 21-26. Development Port Data Register (DPDR)
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Lsb
Table 21-31. BAR Bit Descriptions
The address of the load/store cycle that generated the breakpoint
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Lsb
Chapter 21. Development Support
Development Support Registers
BARV
Unaffected
SPR 159
Description
Data
Unaffected
SPR 630
31
31
21-61
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