Motorola MPC533 Reference Manual page 276

Reset Configuration
Bits Name
0 EARB External Arbitration — Refer to Section 9.5.7, "Arbitration Phase," for a detailed description of Bus
arbitration. The default value is that internal arbitration hardware is used.
0 Internal arbitration is performed
1 External arbitration is assumed
1 IP Initial Interrupt Prefix — This bit defines the initial value of the MSR
MSR
the IP is one, then the MSR
information.
0 MSR[IP] = 0 after reset
1 MSR[IP] = 1 after reset
2 BDRV Bus Pins Drive Strength — This bit determines the bus pins (address, data and control) driving
capability to be either full or reduced drive. The bus default drive strength is full; Upon default, it
also effects the CLKOUT drive strength to be full. See Table 6-7 for more information. BDRV
controls the default state of COM[1] in the SIUMCR.
0 Full drive
1 Reduced drive
3 BDIS Boot Disable — If the BDIS bit is set, then memory controller is not activated after reset. If it is
cleared then the memory controller bank 0 is active immediately after reset such that it matches
any addresses. If a write to the OR0 register occurs after reset this bit definition is ignored. The
default value is that the memory controller is enabled to control the boot with the CS[0] pin. See
Section 10.7, "Global (Boot) Chip-Select Operation," for more information.
0 Memory controller bank 0 is active and matches all addresses immediately after reset
1 Memory controller is not activated after reset.
4:5 BPS Boot Port Size — This field defines the port size of the boot device on reset (BR0[PS]). If a write
to the OR0 register occurs after reset this field definition is ignored. See Table 10-6 and
Table 10-9 for more information.
00 32-bit port (default)
01 8-bit port
10 16-bit port
11 Reserved
6:8 — Reserved. These bits must not be high in the reset configuration word.
9:10 DBGC[0:1] Debug Pins Configuration — See Section 6.2.2.1.1, "SIU Module Configuration Register
(SIUMCR)," for this field definition. The default value is that these pins function as: VFLS[0:1], BI,
BR, BG and BB. See Table 6-8.
11 — Reserved.
12 ATWC Address Type Write Enable Configuration — The default value is that these pins function as WE
pins.
0 WE[0:3]/BE[0:3]/AT[0:3] functions as WE[0:3]/BE[0:3]
1 WE[0:3]/BE[0:3]/AT[0:3] functions as AT[0:3]
See Table 6-7.
13:14 EBDF External Bus Division Factor — This field defines the initial value of the external bus frequency.
The default value is that CLKOUT frequency is equal to that of the internal clock (no division). See
Table 8-9.
15 — Reserved. This bit must be 0 in the reset configuration word.
16 PRPM Peripheral Mode Enable — This bit determines if the chip is in peripheral mode. A detailed
description is in Table 6-13 The default value is no peripheral mode enabled.
7-12
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 7-5. RCW Bit Descriptions
bit defines the Interrupt Table location. If IP is zero then the MSR
IP
initial value is one. Default value is zero. See Table 3-12 for more
IP
MPC533 Reference Manual
Description
immediately after reset. The
IP
initial value is zero, If
IP
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