Motorola MPC533 Reference Manual page 223

UIMB module (which has its own interrupt controller) or from the IMB3 bus (directly from
IMB modules) and from external pins IRQ[0:7].
IRQ[0:7]
UIMB
IMB3
Levels[0:7]
ilbs[0:1]
If programmed to generate an interrupt, the SWT and external pin IRQ[0] always generate
an NMI, non-maskable interrupt to the RCPU.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
EDGE
DET
U-bus INT Levels [0:7]
Timers,
Change
of Lock
SIUMCR
[EICEN, LPMASKEN]
LPMASKEN
IMBIRQ
Sequencer
Figure 6-3. MPC533 Interrupt Structure
Chapter 6. System Configuration and Protection
System Configuration and Protection Features
DEC_IRQ to RCPU
DEC
SWT NMI
GEN
I0
Level 7
Wake up from
I7
low-power mode
Level 6
I6
Level5
16
I5
Level 4
I4
Level 3
I3
Level 2
I2
Level 1
I1
Level 0
I0
Internal
Bus
48
NMI to RCPU
IRQOUT
MUX
IREQ to RCPU
EICEN
6
BBC/IMPU
Offset in
branch table
USIU
6-9