Motorola MPC533 Reference Manual page 767

17.9.8.5 MDASM Status/Control Register (MDASMSCR)
The status and control register gathers a read only bit reflecting the status of the MDASM
signal as well as read/write bits related to its control and configuration.
The signal input status bit reflects the status of the corresponding signal when in input
mode. When in output mode, the PIN bit only reflects the status of the output flip-flop.
MSB 1
0
Field PIN WOR FREN
SRESET —
Addr 0x30 605E, 0x30 6066, 0x30 606E, 0x30 6076, 0x30 607E, 0x30 60DE, 0x30 60E6, 0x30 60EE,
Figure 17-23. MDASM Status/Control Register (MDASMSCR)
Bits Name
0 PIN Pin Input Status — The pin input status bit reflects the status of the corresponding bit.
1 WOR Wired-OR bit — In the DIS, IPWM, IPM and IC modes, the WOR bit is not used; reading this bit
returns the value that was previously written.
In the OCB, OCAB and OPWM modes, the WOR bit selects whether the output buffer is
configured for open-drain or totem pole operation.
1 Output buffer is open-drain.
0 Output buffer is totem pole.
The WOR bit is cleared by reset.
2 FREN Freeze enable bit — This active high read/write control bit enables the MDASM to recognize the
MIOB freeze signal.
1 = The MDASM is frozen if the MIOB freeze line is active.
0 = The MDASM is not frozen even if the MIOB freeze line is active.
The FREN is cleared by reset.
3 — Reserved
4 EDPOL Polarity bit — In the DIS mode, this bit is not used; reading it returns the last value written.
In the IPWM mode, this bit is used to select the capture edge sensitivity of channels A and B.
1 Channel A captures on a falling edge. Channel B captures on a rising edge.
0 Channel A captures on a rising edge. Channel B captures on a falling edge.
In the IPM and IC modes, the EDPOL bit is used to select the input capture edge sensitivity of
channel A.
1 Channel A captures on a falling edge.
0 Channel A captures on a rising edge.
In the OCB, OCAB and OPWM modes, the EDPOL bit is used to select the voltage level on the
output signal.
1 The complement of the output flip-flop logic level appears on the output signal: a match on
channel A resets the output signal; a match on channel B sets the output signal.
0 The output flip-flop logic level appears on the output signal: a match on channel A sets the
output signal, a match on channel B resets the output signal.
The EDPOL bit is cleared by reset.
MOTOROLA Chapter 17. Modular Input/Output Subsystem (MIOS14)
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2 3 4 5
— EDPOL FORCA FORCB
0x30 60F6, 0x30 60FE
Table 17-22. MDASMSCR Bit Descriptions
MIOS14 Double Action Submodule (MDASM)
6 7 8 9
— BSL
000_0000_0000_0000
Description
10 11 12 13 14
— MODE
LSB
15
17-43