Motorola MPC533 Reference Manual page 452

Programming the QADC64E Registers
In stop mode:
• BIU state machine and logic do not shut down
• The CCW and result is not reset and is not accessible
• The module configuration register (QADCMCR), the interrupt register
(QADCINT), and the test register (QADCTEST) are fully accessible and are not
reset
• The data direction register (DDRQA), port data register (PORTQA), and control
register 0 (QACR0) are not reset and are read-only accessible
• Control register 1 (QACR1), control register 2 (QACR2), and the status registers
(QASR0 and QASR1) are reset and are read-only accessible
• In addition, the periodic/interval timer is held in reset during stop mode
If the STOP bit is clear, stop mode is disabled.
13.3.1.2 Freeze Mode
Freeze mode occurs when the background debug mode is enabled in the USIU and a
breakpoint is encountered. This is indicated by the assertion of the internal FREEZE line
on the IMB3. The FRZ bit in the QADCMCR determines whether or not the QADC64E
responds to an IMB3 internal FREEZE signal assertion. Freeze is very useful when
debugging an application.
When the internal FREEZE signal is asserted and the FRZ bit is set, the QADC64E finishes
any conversion in progress and then freezes. Depending on when the FREEZE signal is
asserted, there are three possible queue "freeze" scenarios:
• When a queue is not executing, the QADC64E freezes immediately
• When a queue is executing, the QADC64E completes the conversion in progress and
then freezes
• If, during the execution of the current conversion, the queue operating mode for the
active queue is changed, or a queue 2 abort occurs, the QADC64E freezes
immediately
During freeze mode, both the analog clock, QCLK, and periodic/interval timer are held in
reset. When the QADC64E enters the freeze mode while a queue is active, the current CCW
location of the queue pointer is saved.
During freeze, the analog clock, QCLK, is held in reset and the periodic/interval timer is
held in reset. External trigger events that occur during the freeze mode are not captured. The
BIU remains active to allow IMB3 access to all QADC64E registers and RAM. Although
the QADC64E saves a pointer to the next CCW in the current queue, the software can force
the QADC64E to execute a different CCW by writing new queue operating modes for
normal operation. The QADC64E looks at the queue operating modes, the current queue
13-8
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC533 Reference Manual MOTOROLA