Motorola MPC533 Reference Manual page 36

Figure
Number
4-7 BBC Module Configuration Register (BBCMCR)................................................... 4-16
4-8 Region Base Address Register (MI_RBA[0:3]) ....................................................... 4-19
4-9 Region Attribute Register (MI_RA0[0:3]) ............................................................... 4-19
4-10 Global Region Attribute Register (MI_GRA) .......................................................... 4-21
4-11 External Interrupt Relocation Table Base Address Register (EIBADR) .................. 4-22
5-1 USIU Block Diagram.................................................................................................. 5-3
6-1 System Configuration and Protection Logic............................................................... 6-3
6-2 Circuit Paths of Reading and Writing to SGPIO......................................................... 6-8
6-3 MPC533 Interrupt Structure........................................................................................ 6-9
6-4 Lower Priority Request Masking—One Bit Diagram............................................... 6-14
6-5 MPC533 Interrupt Controller Block Diagram .......................................................... 6-16
6-6 Typical Interrupt Handler Routine ............................................................................ 6-18
6-7 RTC Block Diagram.................................................................................................. 6-21
6-8 PIT Block Diagram ................................................................................................... 6-22
6-9 SWT State Diagram .................................................................................................. 6-23
6-10 SWT Block Diagram................................................................................................. 6-24
6-11 MPC533 Memory Map ............................................................................................. 6-25
6-12 SIU Module Configuration Register (SIUMCR) ...................................................... 6-26
6-13 Internal Memory Mapping Register (IMMR)........................................................... 6-29
6-14 External Master Control Register (EMCR) .............................................................. 6-31
6-15 SIU Interrupt Pending Register (SIPEND) ............................................................... 6-33
6-16 SIU Interrupt Pending Register 2 (SIPEND2) .......................................................... 6-33
6-17 SIU Interrupt Pending Register 3 (SIPEND3) .......................................................... 6-34
6-18 SIU Interrupt Mask Register (SIMASK) .................................................................. 6-35
6-19 SIU Interrupt Mask Register 2 (SIMASK2) ............................................................. 6-35
6-20 SIU Interrupt Mask Register 3 (SIMASK3) ............................................................. 6-36
6-21 SIU Interrupt Edge Level Register (SIEL) ............................................................... 6-36
6-23 Example of SIVEC Register Usage for Interrupt Table Handling............................ 6-37
6-22 SIU Interrupt Vector Register (SIVEC) .................................................................... 6-37
6-24 Interrupt In-Service Register 2 (SISR2).................................................................... 6-38
6-25 Interrupt In-Service Register 3 (SISR3).................................................................... 6-38
6-26 System Protection Control Register (SYPCR).......................................................... 6-39
6-27 Software Service Register (SWSR) .......................................................................... 6-40
6-28 Transfer Error Status Register (TESR) ..................................................................... 6-40
6-29 Decrementer Register (DEC) .................................................................................... 6-42
6-30 Time Base (Reading) (TB)........................................................................................ 6-42
6-31 Time Base (Writing) (TB)......................................................................................... 6-42
6-32 Time Base Reference Register 0 (TBREF0) ............................................................. 6-43
6-33 Time Base Reference Register 1 (TBREF1) ............................................................. 6-43
6-34 Time Base Control and Status Register (TBSCR) .................................................... 6-43
6-35 Real-Time Clock Status and Control Register (RTCSC) .......................................... 6-44
xxxvi
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Figures
Title
MPC533 Reference Manual
Page
Number
MOTOROLA