Motorola MPC533 Reference Manual page 455

The supervisor-only data space segment contains the QADC64E global registers, which
include the QADCMCR, the QADCTEST, and the QADCINT. The supervisor/unrestricted
space designation for the CCW table, the result word table, and the remaining QADC64E
registers is programmable.
13.3.2 QADC64E Interrupt Register (QADCINT)
QADCINT specifies the priority level of QADC64E interrupt requests. The interrupt level
for queue 1 and queue 2 may be different. The interrupt register is read/write accessible in
supervisor data space only. The implemented interrupt register fields can be read and
written, reserved bits read zero and writes have no effect. They are typically written once
when the software initializes the QADC64E, and not changed afterwards.
MSB 1
0
Field IRL1
SRESET
Addr
Figure 13-4. QADC Interrupt Register (QADCINT)
Bit(s) Name
0:4 IRL1 Queue 1 Interrupt Request Level — The IRL1 field establishes the queue 1 interrupt request level.
The 00000 state provides a level 0 interrupt, while 11111 provides a level 31 interrupt. All
interrupts are presented on the IMB3. Interrupt level priority software determines which level has
the highest priority request.
5:9 IRL2 Queue 2 Interrupt Request Level — The IRL2 field establishes the queue 2 interrupt request level.
The 00000 state provides a level 0 interrupt, while 11111 provides a level 31 interrupt. All
interrupts are presented on the IMB3. Interrupt level priority software determines which level has
the highest priority request.
10:15 — Reserved.
The QADC64E conditionally generates interrupts to the bus master via the IMB3 IRQ
signals. When the QADC64E sets a status bit assigned to generate an interrupt, the
QADC64E drives the IRQ bus. The value driven onto IRQ[7:0] represents the interrupt
level assigned to the interrupt source. Under the control of ILBS, each interrupt request
level is driven during the time multiplexed bus during one of four different time slots, with
eight levels communicated per time slot. No hardware priority is assigned to interrupts.
Furthermore, if more than one source on a module requests an interrupt at the same level,
the system software must assign a priority to each source requesting at that level.
Figure 13-5 displays the interrupt levels on IRQ with ILBS. Refer to Chapter 12, "U-Bus
to IMB3 Bus Interface (UIMB)," for more information.
MOTOROLA Chapter 13. Queued Analog-to-Digital Converter Legacy Mode Operation
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2 3 4 5
0x30 4804 (QADCINT_A)
Table 13-3. QADCINT Bit Descriptions
Programming the QADC64E Registers
6 7 8 9
IRL2
0000_0000_0000_0000
Description
10 11 12 13
—
14 LSB
15
13-11