Motorola MPC533 Reference Manual page 363

• If the reservation flag is set, the buses interface acknowledges the cycle in a normal
way
• If the reservation flag is reset, the bus interface should assert the KR. However, the
bus interface should not perform the remote bus write-access or abort it if the remote
bus supports aborted cycles. In this case the failure of the stwcx instruction is
reported to the RCPU.
9.5.11 Bus Exception Control Cycles
The MPC533 bus architecture requires assertion of TA from an external device to signal
that the bus cycle is complete. TA is not asserted in the following cases:
• The external device does not respond
• Various other application-dependent errors occur
External circuitry can provide TEA when no device responds by asserting TA within an
appropriate period of time after the MPC533 initiates the bus cycle (it can be the internal
bus monitor). This allows the cycle to terminate and the processor to enter
exception-processing for the error condition (each one of the internal masters causes an
internal interrupt under this situation). To properly control termination of a bus cycle for a
bus error, TEA must be asserted at the same time or before TA is asserted. TEA should be
negated before the second rising edge after it was sampled as asserted to avoid the detection
of an error for the next initiated bus cycle. TEA is an open drain pin that allows the
"wired-or" of any different sources of error generation.
9.5.11.1 Retrying a Bus Cycle
When an external device asserts the RETRY signal during a bus cycle, the MPC533 enters
a sequence in which it terminates the current transaction, relinquishes the ownership of the
bus, and retries the cycle using the same address, address attributes, and data (in the case of
a write cycle).
Figure 9-32 illustrates the behavior of the MPC533 when the RETRY signal is detected as
a termination of a transfer. As seen in this figure, in the case when the internal arbiter is
enabled, the MPC533 negates BB and asserts BG in the clock cycle following the retry
detection. This allows any external master to gain bus ownership. In the next clock cycle,
a normal arbitration procedure occurs again. As shown in the figure, the external master did
not use the bus, so the MPC533 initiates a new transfer with the same address and attributes
as before.
In Figure 9-33, the same situation is shown except that the MPC533 is working with an
external arbiter. In this case, in the clock cycle after the RETRY signal is detected asserted,
BR is negated together with BB. One clock cycle later, the normal arbitration procedure
occurs again.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chapter 9. External Bus Interface
Bus Operations
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