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Programming the QADC64E Registers
• Attempts to read a supervisor-only data space when not in the supervisor access
mode and SUPV = 1, causes the bus master to assert a bus error condition. No data
is returned. If SUPV = 0, the QADC64E asserts a bus error condition and no data is
returned.
• Attempts to write to supervisor-only data space when not in the supervisor access
mode and SUPV = 1, causes the bus master to assert a bus error condition. No data
is written. If SUPV = 0, the QADC64E asserts a bus error condition and the register
is not written.
• Attempts to read unimplemented data space in the unrestricted access mode and
SUPV = 1, causes the bus master to assert a bus error condition and no data is
returned. In all other attempts to read unimplemented data space, the QADC64E
causes a bus error condition and no data is returned.
• Attempts to write unimplemented data space in the unrestricted access mode and
SUPV= 1, causes the bus master to assert a bus error condition and no data is written.
In all other attempts to write unimplemented data space, the QADC64E causes a bus
error condition and no data is written.
• Attempts to read assignable data space in the unrestricted access mode when the
space is programmed as supervisor space causes the bus master to assert a bus error
condition and no data is returned.
• Attempts to write assignable data space in the unrestricted access mode when the
space is programmed as supervisor space causes the bus master to assert a bus error
condition and the register is not written.
1
S/U
SUPV Bit
Mode
U
U
S
S
1
S/U = Supervisor/Unrestricted
2
QADC64E bus error = Caused by QADC64E
3
Master bus error = Caused by bus master
4 Access to QADCTEST register will act as a reserved/unimplemented register unless in factory
test mode
The bus master indicates the supervisor and user space access with the function code bits
(FC[2:0]) on the IMB3. For privilege violations, refer to the Chapter 9, "External Bus
Interface" to determine the consequence of a bus error cycle termination.
13-10
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Table 13-2. QADC64E Bus Error Response
Supervisor-Only
Register
0
QADC64E bus error
1
Master bus error
0
Valid access
1
Valid access
MPC533 Reference Manual
Supervisor/
Unrestricted Register
2
4
Valid access
3
3
Master bus error
Valid access
Valid access
Reserved/
Unimplemented
Register
2
QADC64E bus error
3
Master bus error
2
QADC64E bus error
2
QADC64E bus error
MOTOROLA
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