Motorola MPC533 Reference Manual page 232

System Configuration and Protection Features
.
Flow without lower priority
masking enabled
Flow with lower priority
masking enabled
6.1.5 Hardware Bus Monitor
The bus monitor ensures that each bus cycle is terminated within a reasonable period of
time. The USIU provides a bus monitor option to monitor internal to external bus accesses
on the external bus. The monitor counts from transfer start to transfer acknowledge and
from transfer acknowledge to transfer acknowledge within bursts. If the monitor times out,
6-18
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Clearing in-service bit
Figure 6-6. Typical Interrupt Handler Routine
MPC533 Reference Manual
Start
Saving the CPU
context
Masking lower
priority requests
Enabling
Interrupt
Handler body
Clearing interrupt
source
Disabling interrupt
Clearing mask
Restoring the CPU
context
RFI
MOTOROLA