Table of Contents
Advertisement
transfer. The master again drives the next data and asserts or negates the BDIP signal. If the
master does not intend to drive another data beat following the current one, it negates
to indicate to the slave that the next data beat transfer is the last data of the burst-write
transfer.
BDIP has two basic timings: normal and late (see Figure 9-14 and Figure 9-15). In the late
timing mode, assertion of BDIP is delayed by the number of wait states in the first data beat.
This implies that for zero-wait-state cycles, BDIP assertion time is identical in normal and
late modes. Cycles with late BDIP generation can occur only during cycles for which the
memory controller generates TA internally. Refer to Chapter 10, "Memory Controller" for
more information.
In the MPC533, no internal master initiates write bursts. The MPC533 is designed to
perform this kind of transaction in order to support an external master that is using the
memory controller services. Refer to Section 10.8, "Memory Controller External Master
Support."
During the data phase of a burst-read cycle, the master receives data from the addressed
slave. If the master needs more than one data beat, it asserts BDIP. Upon receiving the
second-to-last data beat, the master negates BDIP. The slave stops driving new data after it
receives the negation of the BDIP signal at the rising edge of the clock.
Burst inputs (reads) in the MPC533 are used only for instruction cycles. Data load cycles
are not supported.
Figures 9-12 through 9-21 are examples of various burst cycles, including illustrations of
burst-read and burst-write cycles for both the 16- and 32-bit port sizes.
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Chapter 9. External Bus Interface
Bus Operations
BDIP
9-19
Advertisement
Table of Contents
