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Development Port
Refer to Table 21-15 for DSDO data meaning.
21.4.5
Freeze Signal
The freeze indication means that the processor is in debug mode (i.e., normal processor
execution of user code is frozen). On the MPC533, the freeze state can be indicated by three
different pins. The FRZ signal is generated synchronously with the system clock. This
indication may be used to halt any off-chip device while in debug mode as well as a
handshake means between the debug tool and the debug port. The internal freeze status can
also be monitored through status in the data shifted out of the debug port.
21.4.5.1 SGPIO6/FRZ/PTR Signal
The SGPIOC6/FRZ/PTR signal powers up as the PTR function and its function is
controlled by the GPC bits in the SIUMCR.
21.4.5.2 IWP[0:1]/VFLS[0:1] Signals
The IWP[0:1]/VFLS[0:1] signals power up as the VFLS[0:1] function and their function
can be changed via the DBGC bits in the SIUMCR. They can also be set via the reset
configuration word (See Section 7.5.2, "Hard Reset Configuration Word"). The FRZ state
is indicated by the value 0b11 on the VFLS[0:1] signals.
21.4.5.3 VFLS[0:1]/MPIO32B[3:4] Signals
The VFLS[0:1]/MPIO32B[3:4] signals power up as the MPIO32B[3:4] function and their
function can be changed via the VFLS bit in the MIOS14TPCR register. The FRZ state is
indicated by the value 0b11 on the VFLS[0:1] signals.
21.4.6
Development Port Registers
The development port consists logically of the three registers: development port instruction
register (DPIR), development port data register (DPDR), and trap enable control register
(TECR). These registers are physically implemented as two registers, development port
shift register and trap enable control register. The development port shift register acts as
both the DPIR and DPDR depending on the operation being performed. It is also used as a
temporary holding register for data to be stored into the TECR. These registers are
discussed below in more detail.
21.4.6.1 Development Port Shift Register
The development port shift register is a 35-bit shift register. Instructions and data are shifted
into it serially from DSDI using DSCK (or CLKOUT depending on the debug port clock
mode, refer to Section 21.4.6.4, "Development Port Serial Communications — Clock
21-36
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
MPC533 Reference Manual
MOTOROLA
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