Motorola MPC533 Reference Manual page 61

Table
Number
21-4 Detecting the Trace Buffer Start Point ...................................................................... 21-7
21-5 Fetch Show Cycles Control....................................................................................... 21-8
21-6 VF Instruction Type Encoding ................................................................................ 21-11
21-7 VF Queue Flush Information .................................................................................. 21-12
21-8 VFLS History Buffer Flush Encoding .................................................................... 21-12
21-9 Instruction Watchpoints Programming Options...................................................... 21-21
21-10 Load/Store Data Events .......................................................................................... 21-23
21-11 Load/Store Watchpoints Programming Options ..................................................... 21-23
21-12 Check Stop State and Debug Mode ........................................................................ 21-33
21-13 Trap Enable Data Shifted into Development Port Shift Register ........................... 21-41
21-14 Debug Port Command Shifted Into
Development Port Shift Register........................................................................ 21-41
21-15 Status / Data Shifted Out of Development Port Shift Register ............................... 21-42
21-16 Debug Instructions / Data Shifted into Development Port Shift Register .............. 21-43
21-17 Development Support Programming Model ........................................................... 21-47
21-18 Development Support Registers Read Access Protection....................................... 21-48
21-19 Development Support Registers Write Access Protection...................................... 21-48
21-20 CMPA-CMPD Bit Descriptions .............................................................................. 21-49
21-21 ECR Bit Descriptions.............................................................................................. 21-49
21-22 DER Bit Descriptions.............................................................................................. 21-51
21-23 Breakpoint Counter A Value and Control Register (COUNTA)............................. 21-53
21-24 Breakpoint Counter B Value and Control Register (COUNTB)............................ 21-54
21-25 CMPE–CMPF Bit Descriptions .............................................................................. 21-54
21-26 CMPG-CMPH Bit Descriptions.............................................................................. 21-54
21-27 LCTRL1 Bit Descriptions ....................................................................................... 21-55
21-28 LCTRL2 Bit Descriptions ....................................................................................... 21-56
21-29 ICTRL Bit Descriptions .......................................................................................... 21-59
21-30 ISCT_SER Bit Descriptions.................................................................................... 21-60
21-31 BAR Bit Descriptions ............................................................................................. 21-61
22-1 Public Messages ........................................................................................................ 22-5
22-2 Vendor-Defined Messages ........................................................................................ 22-6
22-3 Terms and Definitions ............................................................................................... 22-7
22-4 OTR Bit Descriptions................................................................................................ 22-9
22-5 Tool-Mapped Register Space .................................................................................... 22-9
22-6 DID Bit Descriptions .............................................................................................. 22-10
22-7 DC Bit Descriptions ................................................................................................ 22-11
22-8 RCPU Development Access Modes ....................................................................... 22-11
22-9 MC Bit Descriptions ............................................................................................... 22-12
22-10 UBA Bit Descriptions ............................................................................................. 22-13
22-11 RWA Read/Write Access Bit Descriptions ............................................................. 22-14
22-12 UDI Bit Descriptions .............................................................................................. 22-16
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Tables
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