Motorola MPC533 Reference Manual page 651

Serial Communication Interface
and the QSPI continues to send interrupt requests to the CPU (assuming SPIFIE is set). The
user may avoid causing CPU interrupts by clearing SPIFIE.
As SPIFIE is buffered, clearing it after the SPIF flag is asserted does not immediately stop
the CPU interrupts, but only prevents future interrupts from this source. To clear the current
interrupt, the CPU must read QSPI register SPSR with SPIF asserted, followed by a write
to SPSR with zero in SPIF (clear SPIF). Execution continues in wraparound mode even
while the QSPI is requesting interrupt service from the CPU. The internal working queue
pointer is incremented to the next address and the commands are executed again. SPE is not
cleared by the QSPI. New receive data overwrites previously received data located in the
receive data segment.
Wraparound mode is properly exited in two ways: a) The CPU may disable wrap-around
mode by clearing WREN. The next time end of the queue is reached, the QSPI sets SPIF,
clears SPE, and stops; and, b) The CPU sets HALT. This second method halts the QSPI after
the current transfer is completed, allowing the CPU to negate SPE. The CPU can
immediately stop the QSPI by clearing SPE; however, this method is not recommended, as
it causes the QSPI to abort a serial transfer in process.
15.6.8 Mode Fault
MODF is asserted by the QSPI when the QSPI is the serial master (MSTR = 1) and the slave
select (PCS[0]/SS) input pin is pulled low by an external driver. This is possible only if the
PCS[0]/SS pin is configured as input by QDDR. This low input to SS is not a normal
operating condition. It indicates that a multimaster system conflict may exist, that another
MCU is requesting to become the SPI network master, or simply that the hardware is
incorrectly affecting PCS[0]/SS. SPE in SPCR1 is cleared, disabling the QSPI. The QSPI
pins revert to control by QPDR. If MODF is set and HMIE in SPCR3 is asserted, the QSPI
generates an interrupt to the CPU.
The CPU may clear MODF by reading SPSR with MODF asserted, followed by writing
SPSR with a zero in MODF. After correcting the mode fault problem, the QSPI can be
re-enabled by asserting SPE.
The PCS[0]/SS pin may be configured as a general-purpose output instead of input to the
QSPI. This inhibits the mode fault checking function. In this case, MODF is not used by
the QSPI.
15.7 Serial Communication Interface
The dual, independent, serial communication interface (DSCI) communicates with external
devices through an asynchronous serial bus. The two SCI modules are functionally
equivalent, except that the SCI1 also provides 16-deep queue capabilities for the transmit
and receive operations. The SCIs are fully compatible with other Motorola SCI systems.
MOTOROLA Chapter 15. Queued Serial Multi-Channel Module 15-45
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE