Motorola MPC533 Reference Manual page 390

Chip-Select Timing
The CSx timing is defined by the setup time required between the address lines and the CE
line. The memory controller allows specification of the CS timing to meet the setup time
required by the peripheral device. This is accomplished through the ACS field in the base
register. In Figure 10-10, the ACS bits are set to 0b11, so CSx is asserted half a clock cycle
after the address lines are valid.
CLOCK
Address
TS
TA
CS
RD/WR
Data
Figure 10-10. Peripheral Devices Basic Timing (ACS = 11, TRLX = 0)
10.3.3 Relaxed Timing Examples
The TRLX field is provided for memory systems that need a more relaxed timing between
signals. When TRLX is set and ACS = 0b00, the memory controller inserts an additional
cycle between address and strobes (CS line and WE/OE).
When TRLX and CSNT are both set in a write to memory, the strobe lines (WE/BE[0:3]
and CS, if ACS = 0b00) are negated one clock earlier than in the regular case.
In the case of a bank selected to work with external transfer
acknowledge (SETA = 1) and TRLX = 1, the memory
controller does not support external devices that provide TA to
complete the transfer with zero wait states. The minimum
access duration in this case equals three clock cycles.
10-14
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
NOTE
MPC533 Reference Manual
ACS = 11
CSNT = 1
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