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Figure
Number
1-1
MPC533 Block Diagram............................................................................................. 1-3
1-2
Recommended Connection Diagram for IRAMSTBY............................................. 1-11
1-3
MPC533 Memory Map ............................................................................................. 1-12
1-4
MPC533 Internal Memory Map................................................................................ 1-13
2-1
MPC533 Signal Groupings ......................................................................................... 2-2
2-2
Pads Module Configuration Register (PDMCR) ...................................................... 2-23
2-3
Pads Module Configuration Register 2 (PDMCR2) ................................................. 2-25
3-1
RCPU Block Diagram................................................................................................. 3-2
3-2
Sequencer Data Path ................................................................................................... 3-4
3-3
RCPU Programming Model ....................................................................................... 3-9
3-4
General-Purpose Registers (GPRs) ........................................................................... 3-13
3-5
Floating-Point Registers (FPRs) ............................................................................... 3-14
3-6
Floating-Point Status and Control Register (FPSCR).............................................. 3-15
3-7
Condition Register (CR) ........................................................................................... 3-17
3-8
Integer Exception Register (XER) ............................................................................ 3-19
3-9
Link Register (LR) .................................................................................................... 3-20
3-10
Count Register (CTR) ............................................................................................... 3-21
3-11
Time Base (Read Only)............................................................................................. 3-21
3-12
Machine State Register (MSR) ................................................................................. 3-22
3-13
DAE/Source Instruction Service Register (DSISR).................................................. 3-24
3-14
Data Address Register (DAR)................................................................................... 3-25
3-15
Time Base (Write Only) ............................................................................................ 3-25
3-16
DEC — Decrementer Register.................................................................................. 3-26
3-17
Machine Status Save/Restore Register 0 (SRR0) ..................................................... 3-27
3-18
Machine Status Save/Restore Register 1 (SRR1) ..................................................... 3-27
3-19
SPRG0–SPRG3 — General Special-Purpose Registers 0–3 .................................... 3-28
3-20
Processor Version Register (PVR) ............................................................................ 3-28
3-21
Floating-Point Exception Cause Register (FPECR) ................................................. 3-29
3-22
Basic Instruction Pipeline ......................................................................................... 3-41
4-1
BBC Module Block Diagram...................................................................................... 4-1
4-2
Exception Table Entries Mapping............................................................................... 4-7
4-3
External Interrupt Vectors Splitting .......................................................................... 4-11
4-4
DECRAM Interfaces Block Diagram ....................................................................... 4-11
4-5
BTB Block Diagram ................................................................................................. 4-14
4-6
MPC533 Memory Map ............................................................................................. 4-15
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Figures
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