Table of Contents
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Table
Number
3-26
Machine Check Exception Processor Actions .......................................................... 3-50
3-27
Register Settings Following a Machine Check Exception........................................ 3-51
3-28
Register Settings Following External Interrupt ....................................................... 3-52
3-29
Register Settings for Alignment Exception ............................................................. 3-53
3-30
Register Settings Following Program Exception ..................................................... 3-56
3-31
Register Settings Following a Floating-Point Unavailable Exception..................... 3-57
3-32
Register Settings Following a Decrementer Exception ........................................... 3-57
3-33
Register Settings Following a System Call Exception............................................. 3-58
3-34
Register Settings Following a Trace Exception ........................................................ 3-59
3-35
Register Settings Following Floating-Point Assist Exceptions ................................ 3-60
3-36
Register Settings Following a Software Emulation Exception ................................. 3-61
3-37
Register Settings Following an Instruction Protection Exception ............................ 3-62
3-38
Register Settings Following a Data Protection Error Exception............................... 3-62
3-39
Register Settings Following a Debug Exception ...................................................... 3-64
3-40
Register Settings for L-Bus Breakpoint Instances .................................................... 3-64
4-1
Exception Addresses Mapping.................................................................................... 4-8
4-2
Exception Relocation Page Offset .............................................................................. 4-9
4-3
BBC SPRs ................................................................................................................. 4-15
4-4
BBCMCR BBC Module Configuration Register Bit Descriptions ......................... 4-17
4-5
MI_RBA[0:3] Registers Bit Descriptions................................................................ 4-19
4-6
MI_RA[0:3] Registers Bit Descriptions .................................................................. 4-20
4-7
Region Size Programming Possible Values .............................................................. 4-20
4-8
MI_GRA Global Region Attribute Register Bits Description ................................. 4-21
4-9
EIBADR External Interrupt Relocation Table Base Address Register Bit
Descriptions.......................................................................................................... 4-23
5-1
USIU Address Map..................................................................................................... 5-3
5-2
USIU Special-Purpose Registers ................................................................................ 5-7
5-3
Hex Address Format for SPR Cycles.......................................................................... 5-8
6-1
USIU Pin Multiplexing Control .................................................................................. 6-4
6-2
SGPIO Configuration.................................................................................................. 6-7
6-3
Priority of Interrupt Sources—Regular Operation.................................................... 6-11
6-4
Priority of Interrupt Sources—Enhanced Operation................................................. 6-12
6-5
Interrupt Latency Estimation for Three Typical Cases ............................................. 6-17
6-6
Decrementer Time-Out Periods ................................................................................ 6-20
6-7
SIUMCR Bit Descriptions ....................................................................................... 6-26
6-8
Debug Pins Configuration......................................................................................... 6-28
6-9
General Pins Configuration....................................................................................... 6-28
6-10
Single-Chip Select Field Pin Configuration.............................................................. 6-28
6-11
Multi-Level Reservation Control Pin Configuration ................................................ 6-29
6-12
IMMR Bit Descriptions ........................................................................................... 6-30
6-13
EMCR Bit Descriptions ........................................................................................... 6-31
liv
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Tables
Title
MPC533 Reference Manual
Page
Number
MOTOROLA
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