Motorola MPC533 Reference Manual page 243

Table 6-11. Multi-Level Reservation Control Pin Configuration
MLRC IRQ[0]/
SGPIOC[0]/
MDO[4]
00 IRQ[0]
01 IRQ[0]
10 SGPIOC0
11 IRQ[0]
1
Operates as MODCK[1] during reset.
2
This is true if MTSC is reset to 0. Otherwise, IRQ[2]/CR/SGPIOC[2]/MTS will function as MTS.
6.2.2.1.2 Internal Memory Map Register (IMMR)
The internal memory map register (IMMR) is a register located within the MPC533 special
register space. The IMMR contains identification of a specific device as well as the base
for the internal memory map. Based on the value read from this register, software can
deduce availability and location of any on-chip system resources.
This register can be read by the mfspr instruction. The ISB field can be written by the mtspr
instruction. The PARTNUM and MASKNUM fields are mask programmed and cannot be
changed.
MSB 1 2
0
Field
16 17 18
Field —
Reset 0000
Addr
2
The reset value is a reset configuration word value extracted from the indicated bits of the internal data bus. Refer to
Section 7.5.2, "Hard Reset Configuration Word (RCW)."
Figure 6-13. Internal Memory Mapping Register (IMMR)
MOTOROLA
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
IRQ[1]/RSV/ IRQ[2]/CR/
SGPIOC[1] SGPIOC[2]/MTS
2
IRQ[1] IRQ[2]
2
RSV CR
SGPIOC[1] SGPIOC[2]
IRQ[1] SGPIOC[2]
3 4 5
PARTNUM
19 20 21 22
FLEN —
1
ID(20) 00
Chapter 6. System Configuration and Protection
Memory Map and Register Definitions
Pin Function
IRQ3/KR/
RETRY /SGPIOC[3]
IRQ[3]
KR/RETRY
2
SGPIOC[3]
2
KR/RETRY
6 7 8 9
23 24 25
— —
2
ID(23) 0000
SPR 638
IRQ4/AT[2]/ IRQ[5]/
SGPIOC[4] SGPIOC[5]/MODCK[1]
IRQ[4] IRQ[5]/MODCK[1]
AT[2] IRQ[5]/ MODCK[1]
SGPIOC[4] SGPIOC[5]/MODCK[1]
AT[2] SGPIOC[5]/MODCK[1]
10 11 12 13
MASKNUM
26 27 28 29
ISB
1
ID(28:30)
1
14 15
30 LSB
31
—
0
6-29