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17.8.5.2 MMCSM Up-Counter Register (MMCSMCNT)
MSB
1
0
Field
Reset
Addr
Figure 17-11. MMCSM Up-Counter Register (MMCSMCNT)
Bits
Name
0:15
CNT
Counter value — These bits are read/write data bits representing the 16-bit value of the
up-counter. It contains the value that is driven onto the 16-bit counter bus.
NOTE: Writing to MMCSMCNT simultaneously writes to MMCSMML.
17.8.5.3 MMCSM Modulus Latch Register (MMCSMML)
MSB
1
2
0
Field
Reset
Addr
Figure 17-12. MMCSM Modulus Latch Register (MMCSMML)
Bits
Name
0:15
ML
Modulus latches — These bits are read/write data bits containing the 16-bit modulus value to be
loaded into the up-counter.
The value loaded in this register must be the one's complement of the desired modulus count.
The up-counter increments from this one's complement value up to 0xFFFF to get the correct
number of steps before an overflow is generated to reload the modulus value into the up-counter.
17.8.5.4 MMCSM Status/Control Register (MMCSMSCRD)
(Duplicated)
The MMCSMSCRD and the MMCSMSCR are the same registers accessed at two different
addresses. Reading or writing to one of these two addresses has exactly the same effect.
The duplication of the SCR register allows coherent 32-bit accesses when using a RCPU.
The user should not write directly to the address of the
MMCSMSCRD. This register's address may be reserved for
future use and should not be accessed by the software to ensure
future software compatibility.
MOTOROLA
Chapter 17. Modular Input/Output Subsystem (MIOS14)
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
2
3
4
5
0x30 6030, 0x30 6038, 0x30 6040, 0x30 60B0, 0x30 60B8, 0x30 60C0
Table 17-11. MMCSMCNT Bit Descriptions
3
4
5
0x30 6032, 0x30 603A, 0x30 6042, 0x30 60B2, 0x30 60BA, 0x30 60C2
Table 17-12. MMCSMML Bit Descriptions
WARNING
MIOS14 Modulus Counter Submodule (MMCSM)
6
7
8
9
CNT
Undefined
Description
6
7
8
9
ML
Undefined
Description
10
11
12
13
10
11
12
13
14
LSB
15
14
LSB
15
17-23
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