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Internal Clock Signals
synchronizes these signals to each other. The PITRTCLK frequency and source are
specified by the RTDIV and RTSEL bits in the SCCR. When the backup clock is
functioning as the system clock, the backup clock is automatically selected as the time base
clock source and is twice the MPC533 system clock.
GCLK1
GCLK2
GCLK1_50
(EBDF = 00)
GCLK2_50
(EBDF = 00)
CLKOUT
(EBDF = 00)
GCLK1_50
(EBDF = 01)
GCLK2_50
(EBDF = 01)
CLKOUT
(EBDF = 01)
T1
T2
T3
T4
Note that GCLK1_50, GCLK2_50, and CLKOUT can have a lower frequency than
GCLK1 and GCLK2. This is to enable the external bus operation at lower frequencies
(controlled by EBDF in the SCCR). GCLK2_50 always rises simultaneously with GCLK2.
When DFNH = 0, GCLK2_50 has a 50% duty cycle. With other values of DFNH or DFNL,
the duty cycle is less than 50%. Refer to Figure 8-7. GCLK1_50 rises simultaneously with
GCLK1. When the MPC533 is not in gear mode, the falling edge of GCLK1_50 occurs in
8-8
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Figure 8-4. MPC533 Clocks
MPC533 Reference Manual
MOTOROLA
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