Motorola MPC533 Reference Manual page 12

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Number
9.5.2.2 Single Beat Write Flow.............................................................................. 9-12
9.5.2.3 Single Beat Flow with Small Port Size...................................................... 9-14
9.5.3 Data Bus Pre-Discharge Mode ...................................................................... 9-15
9.5.3.1 Operating Conditions................................................................................. 9-16
9.5.3.2 Initialization Sequence............................................................................... 9-16
9.5.4 Burst Transfer ................................................................................................ 9-17
9.5.5 Burst Mechanism ........................................................................................... 9-18
9.5.6 Alignment and Packaging of Transfers.......................................................... 9-30
9.5.7 Arbitration Phase ........................................................................................... 9-32
9.5.7.1 Bus Request ............................................................................................... 9-33
9.5.7.2 Bus Grant ................................................................................................... 9-33
9.5.7.3 Bus Busy.................................................................................................... 9-34
9.5.7.4 nternal Bus Arbiter .................................................................................... 9-35
9.5.8 Address Transfer Phase Signals..................................................................... 9-37
9.5.8.1 Transfer Start ............................................................................................. 9-38
9.5.8.2 Address Bus ............................................................................................... 9-38
9.5.8.3 Read/Write ................................................................................................. 9-38
9.5.8.4 Burst Indicator ........................................................................................... 9-38
9.5.8.5 Transfer Size .............................................................................................. 9-39
9.5.8.6 Address Types............................................................................................ 9-39
9.5.8.7 Burst Data in Progress ............................................................................... 9-41
9.5.9 Termination Signals ....................................................................................... 9-42
9.5.9.1 Transfer Acknowledge............................................................................... 9-42
9.5.9.2 Burst Inhibit ............................................................................................... 9-42
9.5.9.3 Transfer Error Acknowledge ..................................................................... 9-42
9.5.9.4 Termination Signals Protocol .................................................................... 9-42
9.5.10 Storage Reservation ....................................................................................... 9-44
9.5.11 Bus Exception Control Cycles....................................................................... 9-47
9.5.11.1 Retrying a Bus Cycle ................................................................................. 9-47
9.5.11.2 Termination Signals Protocol Summary.................................................... 9-51
9.5.12 Bus Operation in External Master Modes...................................................... 9-51
9.5.13 Contention Resolution on External Bus ........................................................ 9-55
9.5.14 Show Cycle Transactions............................................................................... 9-57
10.1 Overview............................................................................................................ 10-1
10.2 Memory Controller Architecture ....................................................................... 10-3
10.2.1 Associated Registers ...................................................................................... 10-4
10.2.2 Port Size Configuration ................................................................................. 10-5
10.2.3 Write-Protect Configuration .......................................................................... 10-5
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PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Contents
Title
Chapter 10
Memory Controller
MPC533 Reference Manual
Page
Number
MOTOROLA