Motorola MPC533 Reference Manual page 892

Watchpoints and Breakpoints Support
Comparator A
eq
lt
Comparator B
eq
lt
Comparator C
eq
lt
Comparator D
eq
lt
Figure 21-4. Instruction Support General Structure
21.2.2.1 Load/Store Support
There are two load/store address comparators E, and F. Each compares the 32 address bits
and the cycle's attributes (read/write). The two least-significant bits are masked (ignored)
whenever a word is accessed and the least-significant bit is masked whenever a half-word
is accessed. (For more information refer to Section 21.2.1.2, "Byte and Half-Word Working
Modes"). Each comparator generates two output signals: equal and less than. These signals
are used to generate one of the following four events (one from each comparator): equal,
not equal, greater than, less than.
There are two load/store data comparators (comparators G,H) each is 32 bits wide and can
be programmed to treat numbers either as signed values or as unsigned values. Each data
comparator operates as four independent byte comparators. Each byte comparator has a
mask bit and generates two output signals: equal and less than, if the mask bit is not set.
Therefore, each 32 bit comparator has eight output signals.
21-22
PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE
Compare Type
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Type
Logic
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Type
Logic
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Type
Logic
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Type
Logic
MPC533 Reference Manual
Control Bits
A
B
(A & B)
(A | B)
AND-OR
C
Logic
D
(C & D)
(C | D)
I-Watchpoint 0
I-Watchpoint 1
I-Watchpoint 2
I-Watchpoint 3
I-Breakpoint
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